From 902dc0e01ffc5f215eabde8e0428ce462db18a73 Mon Sep 17 00:00:00 2001 From: Sona Mathew Date: Thu, 23 May 2024 16:02:27 -0500 Subject: [PATCH] fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE Implements mitigation for CVE-2024-5660 that affects Cortex-A78_AE revisions r0p0, r0p1, r0p2, r0p3. The workaround is to disable the hardware page aggregation at EL3 by setting CPUECTLR_EL1[46] = 1'b1. Public Documentation: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660 Change-Id: I33ac653fcb45f687fe9ace1c76a3eb2000459751 Signed-off-by: Sona Mathew --- lib/cpus/aarch64/cortex_a78_ae.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index bc10186ff..7fa1f9bcd 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -22,6 +22,13 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae #endif /* WORKAROUND_CVE_2022_23960 */ +/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ +workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 + sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46) +workaround_reset_end cortex_a78_ae, CVE(2024, 5660) + +check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3) + workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 workaround_reset_end cortex_a78_ae, ERRATUM(1941500)