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Merge "fix(intel): add in missing ECC register" into integration

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Yann Gautier 2024-08-23 14:45:12 +02:00 • committed by TrustedFirmware Code Review
commit 8fb91783ff
2 changed files with 3 additions and 0 deletions
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2
plat/intel/soc/agilex5/include/agilex5_system_manager.h
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -147,6 +148,7 @@
/* QSPI ECC from SDM register */ /* QSPI ECC from SDM register */
#define SOCFPGA_ECC_QSPI_CTRL 0x08 #define SOCFPGA_ECC_QSPI_CTRL 0x08
#define SOCFPGA_ECC_QSPI_INITSTAT 0x0C
#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10 #define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14 #define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18 #define SOCFPGA_ECC_QSPI_ERRINTENR 0x18

1
plat/intel/soc/common/socfpga_sip_svc.c
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@ -419,6 +419,7 @@ static int is_out_of_sec_range(uint64_t reg_addr)
case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */
case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */
case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */
case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */