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plat/arm: Support for Cortex A5 in FVP Versatile Express platform

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Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.

Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>
This commit is contained in:
Usama Arif 2018-12-12 17:14:29 +00:00
parent a5aa25af65
commit 8f73663b59
5 changed files with 157 additions and 0 deletions
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144
fdts/fvp-ve-Cortex-A5x1.dts Normal file
View file

@ -0,0 +1,144 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
model = "V2P-CA5s";
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x1000000>;
};
hdlcd@2a110000 {
compatible = "arm,hdlcd";
reg = <0x2a110000 0x1000>;
interrupts = <0 85 4>;
clocks = <&oscclk3>;
clock-names = "pxlclk";
};
scu@2c000000 {
compatible = "arm,cortex-a5-scu";
reg = <0x2c000000 0x58>;
};
watchdog@2c000620 {
compatible = "arm,cortex-a5-twd-wdt";
reg = <0x2c000620 0x20>;
interrupts = <1 14 0x304>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
<0x2c000100 0x100>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0: osc@0 {
/* CPU and internal AXI reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <50000000 100000000>;
#clock-cells = <0>;
clock-output-names = "oscclk0";
};
oscclk1: osc@1 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <5000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk1";
};
osc@2 {
/* DDR2 */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <80000000 120000000>;
#clock-cells = <0>;
clock-output-names = "oscclk2";
};
oscclk3: osc@3 {
/* HDLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
freq-range = <23750000 165000000>;
#clock-cells = <0>;
clock-output-names = "oscclk3";
};
osc@4 {
/* Test chip gate configuration */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
freq-range = <80000000 80000000>;
#clock-cells = <0>;
clock-output-names = "oscclk4";
};
smbclk: osc@5 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
freq-range = <25000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk5";
};
};
smb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x04000000>,
<1 0 0x14000000 0x04000000>,
<2 0 0x18000000 0x04000000>,
<3 0 0x1c000000 0x04000000>,
<4 0 0x0c000000 0x04000000>,
<5 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 42 &gic 0 42 4>;
/include/ "rtsm_ve-motherboard-aarch32.dtsi"
};
};

2
include/arch/aarch32/el3_common_macros.S
View file

@ -94,9 +94,11 @@
* from all exception levels.
* ---------------------------------------------------------------------
*/
#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP)
ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT)
vmsr FPEXC, r0
isb
#endif
#if (ARM_ARCH_MAJOR > 7)
/* ---------------------------------------------------------------------

5
make_helpers/armv7-a-cpus.mk
View file

@ -47,4 +47,9 @@ ifeq ($(filter yes,$(ARM_CORTEX_A7) $(ARM_CORTEX_A12) $(ARM_CORTEX_A15) $(ARM_CO
$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
$(eval $(call add_define,ARMV7_SUPPORTS_VIRTUALIZATION))
$(eval $(call add_define,ARMV7_SUPPORTS_GENERIC_TIMER))
$(eval $(call add_define,ARMV7_SUPPORTS_VFP))
endif
ifeq ($(ARM_CORTEX_A5),yes)
$(eval $(call add_define,ARM_CORTEX_A5))
endif

4
plat/arm/board/fvp_ve/fvp_ve_def.h
View file

@ -59,7 +59,11 @@
******************************************************************************/
/* VE compatible GIC memory map */
#define VE_GICD_BASE 0x2c001000
#ifdef ARM_CORTEX_A5
#define VE_GICC_BASE 0x2c000100
#else
#define VE_GICC_BASE 0x2c002000
#endif
#define VE_GICH_BASE 0x2c004000
#define VE_GICV_BASE 0x2c006000

2
plat/arm/common/arm_bl1_setup.c
View file

@ -158,7 +158,9 @@ void arm_bl1_platform_setup(void)
#ifdef ARM_SYS_TIMCTL_BASE
arm_configure_sys_timer();
#endif
#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
write_cntfrq_el0(plat_get_syscnt_freq2());
#endif
}
void bl1_platform_setup(void)