From 3cedc47b1d4cf46622b4b5413fab01d3224dc872 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 30 Apr 2024 11:27:17 +0100 Subject: [PATCH 1/9] feat(tc): add device tree binding for TC4 Since TC3 and TC4 share most components in the hardware design, they can reuse the device tree binding. For this reason, this patch extracts the common modules from tc3.dts and put into the file tc3-4-based.dtsi. As a result, a new created tc4.dts file includes tc3-4-based.dtsi for support DT binding for the TC4 platform. Change-Id: Ib7497162cb131d94a722aeaa14a1a37fb0095829 Signed-off-by: Leo Yan --- fdts/tc3-4-base.dtsi | 84 ++++++++++++++++++++++++++++++++++++++++++++ fdts/tc3.dts | 77 +--------------------------------------- fdts/tc4.dts | 26 ++++++++++++++ 3 files changed, 111 insertions(+), 76 deletions(-) create mode 100644 fdts/tc3-4-base.dtsi create mode 100644 fdts/tc4.dts diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi new file mode 100644 index 000000000..169d68fe7 --- /dev/null +++ b/fdts/tc3-4-base.dtsi @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define LIT_CAPACITY 239 +#define MID_CAPACITY 686 +#define BIG_CAPACITY 1024 + +#define MHU_TX_COMPAT "arm,mhuv3" +#define MHU_TX_INT_NAME "" + +#define MHU_RX_COMPAT "arm,mhuv3" +#define MHU_OFFSET 0x10000 +#define MHU_MBOX_CELLS 3 +#define MHU_RX_INT_NUM 300 +#define MHU_RX_INT_NAME "combined-mbx" + +#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ +#define UARTCLK_FREQ 3750000 + +#if TARGET_FLAVOUR_FVP +#define DPU_ADDR 4000000000 +#define DPU_IRQ 579 +#elif TARGET_FLAVOUR_FPGA +#define DPU_ADDR 2cc00000 +#define DPU_IRQ 69 +#endif +#include "tc-base.dtsi" + +/ { + cpus { + CPU2:cpu@200 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU3:cpu@300 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU6:cpu@600 { + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + }; + + CPU7:cpu@700 { + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + }; + }; + + gic: interrupt-controller@GIC_CTRL_ADDR { + ppi-partitions { + ppi_partition_little: interrupt-partition-0 { + affinity = <&CPU0>, <&CPU1>; + }; + + ppi_partition_mid: interrupt-partition-1 { + affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; + }; + + ppi_partition_big: interrupt-partition-2 { + affinity = <&CPU6>, <&CPU7>; + }; + }; + }; + + sram: sram@6000000 { + cpu_scp_scmi_p2a: scp-shmem@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + firmware { + scmi { + mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; + shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; + }; + }; +}; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 58c8edca0..491cbb608 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -10,67 +10,22 @@ #include #include -#define LIT_CAPACITY 239 -#define MID_CAPACITY 686 -#define BIG_CAPACITY 1024 - #define MHU_TX_ADDR 46040000 /* hex */ -#define MHU_TX_COMPAT "arm,mhuv3" -#define MHU_TX_INT_NAME "" - #define MHU_RX_ADDR 46140000 /* hex */ -#define MHU_RX_COMPAT "arm,mhuv3" -#define MHU_OFFSET 0x10000 -#define MHU_MBOX_CELLS 3 -#define MHU_RX_INT_NUM 300 -#define MHU_RX_INT_NAME "combined-mbx" #define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu" #define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" #define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" -#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ -#define UARTCLK_FREQ 3750000 - -#if TARGET_FLAVOUR_FVP -#define DPU_ADDR 4000000000 -#define DPU_IRQ 579 -#elif TARGET_FLAVOUR_FPGA -#define DPU_ADDR 2cc00000 -#define DPU_IRQ 69 -#endif - #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" #else #include "tc-fpga.dtsi" #endif /* TARGET_FLAVOUR_FVP */ -#include "tc-base.dtsi" +#include "tc3-4-base.dtsi" / { - cpus { - CPU2:cpu@200 { - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; - }; - - CPU3:cpu@300 { - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; - }; - - CPU6:cpu@600 { - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - }; - - CPU7:cpu@700 { - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - }; - }; - cs-pmu@0 { compatible = "arm,coresight-pmu"; reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; @@ -109,36 +64,6 @@ reg = <0x0 0x4f000000 0x0 0x4000000>; }; - sram: sram@6000000 { - cpu_scp_scmi_p2a: scp-shmem@80 { - compatible = "arm,scmi-shmem"; - reg = <0x80 0x80>; - }; - }; - - firmware { - scmi { - mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; - shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; - }; - }; - - gic: interrupt-controller@GIC_CTRL_ADDR { - ppi-partitions { - ppi_partition_little: interrupt-partition-0 { - affinity = <&CPU0>, <&CPU1>; - }; - - ppi_partition_mid: interrupt-partition-1 { - affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; - }; - - ppi_partition_big: interrupt-partition-2 { - affinity = <&CPU6>, <&CPU7>; - }; - }; - }; - #if TARGET_FLAVOUR_FVP smmu_700: iommu@3f000000 { status = "okay"; diff --git a/fdts/tc4.dts b/fdts/tc4.dts new file mode 100644 index 000000000..750344c1f --- /dev/null +++ b/fdts/tc4.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +#include +#include +#include + +#define MHU_TX_ADDR 46240000 /* hex */ +#define MHU_RX_ADDR 46250000 /* hex */ + +#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" +#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" +#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" + +#include "tc-common.dtsi" +#if TARGET_FLAVOUR_FVP +#include "tc-fvp.dtsi" +#else +#include "tc-fpga.dtsi" +#endif /* TARGET_FLAVOUR_FVP */ +#include "tc3-4-base.dtsi" From 36ffe3e1be3fe91e2b709b769eb4f17545f6ce04 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 10 May 2024 11:00:33 +0100 Subject: [PATCH 2/9] feat(tc): add MHUv3 register addresses for TC4 Change-Id: I06351fc048d792943f338291f8f64827339e8e1c Signed-off-by: Leo Yan --- plat/arm/board/tc/include/platform_def.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index 45d17ba9e..57bb55e25 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -306,6 +306,9 @@ #elif TARGET_PLATFORM == 3 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000) +#elif TARGET_PLATFORM == 4 +#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) +#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49010000) #endif #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 From e8e1b60820dcba1f2be151d296a8e81de9bed8ba Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Thu, 14 Dec 2023 14:32:40 +0000 Subject: [PATCH 3/9] feat(tc): allow TARGET_VERSION=4 Add basic support for TARGET_VERSION=4. It extends the existing 'if' statements in the Makefile and the header to allow them to take the value of 4 and also specifies the SCMI platform info to use for TC4. Change-Id: I8d8257671314277a133e88ef65fae8fada93d00e Signed-off-by: Jackson Cooper-Driver Signed-off-by: Leo Yan --- plat/arm/board/tc/include/platform_def.h | 8 ++++---- plat/arm/board/tc/include/tc_helpers.S | 4 ++++ plat/arm/board/tc/platform.mk | 11 +++++++++-- plat/arm/board/tc/tc_bl31_setup.c | 4 +++- 4 files changed, 20 insertions(+), 7 deletions(-) diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index 57bb55e25..fb3d1f1aa 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -230,9 +230,9 @@ #if TARGET_PLATFORM <= 2 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) -#elif TARGET_PLATFORM == 3 +#elif TARGET_PLATFORM >= 3 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) -#endif /* TARGET_PLATFORM == 3 */ +#endif /* TARGET_PLATFORM >= 3 */ #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) @@ -294,9 +294,9 @@ /* Message Handling Unit (MHU) base addresses */ #if TARGET_PLATFORM <= 2 #define PLAT_CSS_MHU_BASE UL(0x45400000) -#elif TARGET_PLATFORM == 3 +#elif TARGET_PLATFORM >= 3 #define PLAT_CSS_MHU_BASE UL(0x46000000) -#endif /* TARGET_PLATFORM == 3 */ +#endif /* TARGET_PLATFORM >= 3 */ #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE /* AP<->RSS MHUs */ diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S index 29130eaab..9adf09afd 100644 --- a/plat/arm/board/tc/include/tc_helpers.S +++ b/plat/arm/board/tc/include/tc_helpers.S @@ -81,6 +81,10 @@ func TC_HANDLER(3) ret endfunc TC_HANDLER(3) +func TC_HANDLER(4) + ret +endfunc TC_HANDLER(4) + /* ----------------------------------------------------- * void plat_reset_handler(void); * ----------------------------------------------------- diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 1a7289a5f..7e0464cd8 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -61,8 +61,8 @@ ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0) Some of the features might not work as expected) endif -ifeq ($(shell expr $(TARGET_PLATFORM) \<= 3), 0) - $(error TARGET_PLATFORM must be less than or equal to 3) +ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0) + $(error TARGET_PLATFORM must be less than or equal to 4) endif ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),) @@ -127,6 +127,13 @@ TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ lib/cpus/aarch64/cortex_x925.S endif +# CPU libraries for TARGET_PLATFORM=4 +ifeq (${TARGET_PLATFORM}, 4) +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_gelas.S \ + lib/cpus/aarch64/nevis.S \ + lib/cpus/aarch64/travis.S +endif + INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c \ plat/arm/common/arm_ni.c diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c index 53404dfcc..801872aa9 100644 --- a/plat/arm/board/tc/tc_bl31_setup.c +++ b/plat/arm/board/tc/tc_bl31_setup.c @@ -58,7 +58,7 @@ static scmi_channel_plat_info_t tc_scmi_plat_info = { .db_modify_mask = 0x1, .ring_doorbell = &mhuv2_ring_doorbell, }; -#elif TARGET_PLATFORM == 3 +#elif TARGET_PLATFORM >= 3 static scmi_channel_plat_info_t tc_scmi_plat_info = { .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), @@ -66,7 +66,9 @@ static scmi_channel_plat_info_t tc_scmi_plat_info = { .db_modify_mask = 0x1, .ring_doorbell = &mhu_ring_doorbell, }; +#endif +#if TARGET_PLATFORM == 3 static void enable_ns_mcn_pmu(void) { /* From d6b6a8b7cc9fa872f752640a52b9a752fa50e3a8 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Mon, 22 Apr 2024 17:18:14 +0100 Subject: [PATCH 4/9] feat(tc): add system generic timer register definition for TC4 Add new include (specific to TC4) to the TC platform file which specifies the system generic timer base address and is used by the TF-a for use as system counters. Note that this include must come before arm_def.h. This is required as it checks if ARM_SYS_CNTCTL macros are defined before defining its own macros. Change-Id: I56861e5737271b29f09c75d962533be620766b52 Signed-off-by: Jackson Cooper-Driver Signed-off-by: Leo Yan --- plat/arm/board/tc/include/platform_def.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index fb3d1f1aa..0652148b1 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -12,7 +12,21 @@ #include #include #include + +/* + * arm_def.h depends on the platform system counter macros, so must define the + * platform macros before including arm_def.h. + */ +#if TARGET_PLATFORM == 4 +#ifdef ARM_SYS_CNTCTL_BASE +#error "error: ARM_SYS_CNTCTL_BASE is defined prior to the PLAT_ARM_SYS_CNTCTL_BASE definition" +#endif +#define PLAT_ARM_SYS_CNTCTL_BASE UL(0x47000000) +#define PLAT_ARM_SYS_CNTREAD_BASE UL(0x47010000) +#endif + #include + #include #include #include From e9e83e96bb0f7d83dd7e8eae3a3a82f391922bd9 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Wed, 24 Apr 2024 10:27:58 +0100 Subject: [PATCH 5/9] feat(tc): add new TC4 RoS definitions The TC4 uses a new RoS (Virtual Peripherals) and places them at different address to that in TC3. Add these addresses to the DTS. Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe Signed-off-by: Jackson Cooper-Driver Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 19 +++++++++---------- fdts/tc-fpga.dtsi | 4 ++-- fdts/tc-fvp.dtsi | 22 +++++++++++----------- fdts/tc2.dts | 20 ++++++++++++++++++++ fdts/tc3.dts | 20 ++++++++++++++++++++ fdts/tc4.dts | 20 ++++++++++++++++++++ 6 files changed, 82 insertions(+), 23 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index fc6fe78b1..f191e2951 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -437,9 +437,9 @@ }; - ethernet: ethernet@18000000 { - reg = <0x0 0x18000000 0x0 0x10000>; - interrupts = ; + ethernet: ethernet@ETHERNET_ADDR { + reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>; + interrupts = ; reg-io-width = <2>; smsc,irq-push-pull; @@ -452,10 +452,9 @@ clock-output-names = "bp:clock24mhz"; }; - - sysreg: sysreg@1c010000 { + sysreg: sysreg@SYS_REGS_ADDR { compatible = "arm,vexpress-sysreg"; - reg = <0x0 0x001c010000 0x0 0x1000>; + reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>; gpio-controller; #gpio-cells = <2>; }; @@ -468,11 +467,11 @@ regulator-always-on; }; - mmci: mmci@1c050000 { + mmci: mmci@MMC_ADDR { compatible = "arm,pl180", "arm,primecell"; - reg = <0x0 0x001c050000 0x0 0x1000>; - interrupts = , - ; + reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>; + interrupts = , + ; wp-gpios = <&sysreg 1 0>; bus-width = <4>; max-frequency = <25000000>; diff --git a/fdts/tc-fpga.dtsi b/fdts/tc-fpga.dtsi index 73f47431f..08b9ae560 100644 --- a/fdts/tc-fpga.dtsi +++ b/fdts/tc-fpga.dtsi @@ -25,12 +25,12 @@ stdout-path = "serial0:38400n8"; }; - ethernet: ethernet@18000000 { + ethernet: ethernet@ETHERNET_ADDR { compatible = "smsc,lan9115"; phy-mode = "mii"; }; - mmci: mmci@1c050000 { + mmci: mmci@MMC_ADDR { non-removable; }; }; diff --git a/fdts/tc-fvp.dtsi b/fdts/tc-fvp.dtsi index 1e14f0bcb..f57e21da0 100644 --- a/fdts/tc-fvp.dtsi +++ b/fdts/tc-fvp.dtsi @@ -43,26 +43,26 @@ stdout-path = "serial0:115200n8"; }; - ethernet: ethernet@18000000 { + ethernet: ethernet@ETHERNET_ADDR { compatible = "smsc,lan91c111"; }; - mmci: mmci@1c050000 { + mmci: mmci@MMC_ADDR { cd-gpios = <&sysreg 0 0>; }; - rtc@1c170000 { + rtc@RTC_ADDR { compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0x1C170000 0x0 0x1000>; - interrupts = ; + reg = <0x0 ADDRESSIFY(RTC_ADDR) 0x0 0x1000>; + interrupts = ; clocks = <&soc_refclk>; clock-names = "apb_pclk"; }; - kmi@1c060000 { + kmi@KMI_0_ADDR { compatible = "arm,pl050", "arm,primecell"; - reg = <0x0 0x001c060000 0x0 0x1000>; - interrupts = ; + reg = <0x0 ADDRESSIFY(KMI_0_ADDR) 0x0 0x1000>; + interrupts = ; clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; clock-names = "KMIREFCLK", "apb_pclk"; }; @@ -75,10 +75,10 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - virtio_block@1c130000 { + virtio_block@VIRTIO_BLOCK_ADDR { compatible = "virtio,mmio"; - reg = <0x0 0x1c130000 0x0 0x200>; + reg = <0x0 ADDRESSIFY(VIRTIO_BLOCK_ADDR) 0x0 0x200>; /* spec lists this wrong */ - interrupts = ; + interrupts = ; }; }; diff --git a/fdts/tc2.dts b/fdts/tc2.dts index ae37ce3ff..8344d16e0 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -41,6 +41,26 @@ #define DPU_ADDR 2cc00000 #define DPU_IRQ 69 +#define ETHERNET_ADDR 18000000 +#define ETHERNET_INT 109 + +#define SYS_REGS_ADDR 1c010000 + +#define MMC_ADDR 1c050000 +#define MMC_INT_0 107 +#define MMC_INT_1 108 + +#define RTC_ADDR 1c170000 +#define RTC_INT 100 + +#define KMI_0_ADDR 1c060000 +#define KMI_0_INT 197 +#define KMI_1_ADDR 1c070000 +#define KMI_1_INT 103 + +#define VIRTIO_BLOCK_ADDR 1c130000 +#define VIRTIO_BLOCK_INT 204 + #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 491cbb608..51431c2f6 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -17,6 +17,26 @@ #define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" #define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" +#define ETHERNET_ADDR 18000000 +#define ETHERNET_INT 109 + +#define SYS_REGS_ADDR 1c010000 + +#define MMC_ADDR 1c050000 +#define MMC_INT_0 107 +#define MMC_INT_1 108 + +#define RTC_ADDR 1c170000 +#define RTC_INT 100 + +#define KMI_0_ADDR 1c060000 +#define KMI_0_INT 197 +#define KMI_1_ADDR 1c070000 +#define KMI_1_INT 103 + +#define VIRTIO_BLOCK_ADDR 1c130000 +#define VIRTIO_BLOCK_INT 204 + #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" diff --git a/fdts/tc4.dts b/fdts/tc4.dts index 750344c1f..ef7a08033 100644 --- a/fdts/tc4.dts +++ b/fdts/tc4.dts @@ -17,6 +17,26 @@ #define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" #define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" +#define ETHERNET_ADDR 64000000 +#define ETHERNET_INT 799 + +#define SYS_REGS_ADDR 60080000 + +#define MMC_ADDR 600b0000 +#define MMC_INT_0 778 +#define MMC_INT_1 779 + +#define RTC_ADDR 600a0000 +#define RTC_INT 777 + +#define KMI_0_ADDR 60100000 +#define KMI_0_INT 784 +#define KMI_1_ADDR 60110000 +#define KMI_1_INT 785 + +#define VIRTIO_BLOCK_ADDR 60020000 +#define VIRTIO_BLOCK_INT 769 + #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" From 9face2123a5925619d54070d0a9e4e628084eff3 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Mon, 8 Jan 2024 09:53:04 +0000 Subject: [PATCH 6/9] feat(tc): enable SME and SME2 options for TC4 Set the Make flags for TF-A to be able to enable SME and SME2 features. Note that we enable these architectural features for both the secure and non-secure worlds, which is required on TC4. In the case of the non-secure world, we specify a value of 2 for the flag which specifies that TF-A should check the feature register to ensure that the feature is present before enabling it. This allows these flags to be compatible with all platforms and stops TF-A doing anything different if it does not detect that the feature is present. Change-Id: I51f8c7e3eb1cf06767f4b155c93269e1f129f730 Signed-off-by: Jackson Cooper-Driver Signed-off-by: Leo Yan --- plat/arm/board/tc/platform.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 7e0464cd8..217b2c923 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -26,6 +26,9 @@ BRANCH_PROTECTION := 1 ENABLE_FEAT_MPAM := 1 # default is 2, optimise ENABLE_SVE_FOR_NS := 2 # to show we use it ENABLE_SVE_FOR_SWD := 1 +ENABLE_SME_FOR_NS := 2 +ENABLE_SME2_FOR_NS := 2 +ENABLE_SME_FOR_SWD := 1 ENABLE_TRBE_FOR_NS := 1 ENABLE_SYS_REG_TRACE_FOR_NS := 1 ENABLE_FEAT_AMU := 1 From b3a4f8cfcfad1df90273d0e131c2016068c57f61 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 22 Apr 2024 18:02:52 +0100 Subject: [PATCH 7/9] feat(tc): update DT for Drage GPU This patch incorporates the changes for Drage GPU to uses new access window interface "IRQ_AW". As the interrupt properties are different between TC4 and other TC platforms, this patch appends the interrupt properties in platform specific DT binding file. Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25 Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 4 ---- fdts/tc2.dts | 4 ++++ fdts/tc3.dts | 4 ++++ fdts/tc4.dts | 7 +++++++ 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index f191e2951..be0a9f605 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -495,10 +495,6 @@ gpu: gpu@2d000000 { compatible = "arm,mali-midgard"; reg = <0x0 0x2d000000 0x0 0x200000>; - interrupts = , - , - ; - interrupt-names = "JOB", "MMU", "GPU"; clocks = <&gpu_core_clk>; clock-names = "shadercores"; #if TC_SCMI_PD_CTRL_EN diff --git a/fdts/tc2.dts b/fdts/tc2.dts index 8344d16e0..c49227493 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -291,6 +291,10 @@ }; gpu: gpu@2d000000 { + interrupts = , + , + ; + interrupt-names = "JOB", "MMU", "GPU"; iommus = <&smmu_700 0x200>; }; }; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 51431c2f6..ffe3b6d9c 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -110,6 +110,10 @@ }; gpu: gpu@2d000000 { + interrupts = , + , + ; + interrupt-names = "JOB", "MMU", "GPU"; #if TARGET_FLAVOUR_FVP iommus = <&smmu_700 0x200>; #endif diff --git a/fdts/tc4.dts b/fdts/tc4.dts index ef7a08033..13fabc941 100644 --- a/fdts/tc4.dts +++ b/fdts/tc4.dts @@ -44,3 +44,10 @@ #include "tc-fpga.dtsi" #endif /* TARGET_FLAVOUR_FVP */ #include "tc3-4-base.dtsi" + +/ { + gpu: gpu@2d000000 { + interrupts = ; + interrupt-names = "IRQAW"; + }; +}; From 11ec5de6957206c9b1ec84b78cccf4e876688a84 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 22 Jul 2024 16:53:30 +0100 Subject: [PATCH 8/9] feat(tc): bind GPU SMMU on TC4 A SMMU-700 is used on TC4 for only GPU, on both FVP and FPGA. Add DT binding for it. Change-Id: I1b840676fd02c3961d4efdd769f12a4b01d459fb Signed-off-by: Leo Yan --- fdts/tc4.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fdts/tc4.dts b/fdts/tc4.dts index 13fabc941..8b21be1d9 100644 --- a/fdts/tc4.dts +++ b/fdts/tc4.dts @@ -46,8 +46,13 @@ #include "tc3-4-base.dtsi" / { + smmu_700: iommu@3f000000 { + status = "okay"; + }; + gpu: gpu@2d000000 { interrupts = ; interrupt-names = "IRQAW"; + iommus = <&smmu_700 0x200>; }; }; From e365479d0d89999f815ea71b1511ff7952b479e2 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Tue, 23 Apr 2024 10:04:44 +0100 Subject: [PATCH 9/9] feat(tc): bind DPU SMMU on TC4 TC4 adds a new SMMU-700 specifically for the DPU (in the RoS). This is used as the DPU SMMU instead of the existing SMMU used for both the GPU and DPU. Update the devicetree to reflect this. Note that the streamID values have also changes for this new SMMU. This is because TC4 also updates the new SMMU to use a different streamID for each DPU port - these must all be added to the device tree. Change-Id: If2ce9749e40937fd1291346d071b691cfb662f2e Signed-off-by: Jackson Cooper-Driver Signed-off-by: Leo Yan --- fdts/tc4.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fdts/tc4.dts b/fdts/tc4.dts index 8b21be1d9..135d30a22 100644 --- a/fdts/tc4.dts +++ b/fdts/tc4.dts @@ -50,6 +50,15 @@ status = "okay"; }; + smmu_700_dpu: iommu@4002a00000 { + status = "okay"; + }; + + dp0: display@DPU_ADDR { + iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, + <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; + }; + gpu: gpu@2d000000 { interrupts = ; interrupt-names = "IRQAW";