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fix(intel): fix UART baud rate and clock

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Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353
This commit is contained in:
Sieu Mun Tang 2022-07-01 09:08:57 +08:00 • committed by Sandrine Bailleux
parent 8613c15754
commit 8e53b2fa2e
4 changed files with 5 additions and 9 deletions
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1
plat/intel/soc/agilex/platform.mk
View file

@ -80,5 +80,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1 BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0 BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1 MULTI_CONSOLE_API := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1 USE_COHERENT_MEM := 1

11
plat/intel/soc/common/include/platform_def.h
View file

@ -17,6 +17,7 @@
#define PLAT_SOCFPGA_STRATIX10 1 #define PLAT_SOCFPGA_STRATIX10 1
#define PLAT_SOCFPGA_AGILEX 2 #define PLAT_SOCFPGA_AGILEX 2
#define PLAT_SOCFPGA_N5X 3 #define PLAT_SOCFPGA_N5X 3
#define PLAT_SOCFPGA_EMULATOR 0
/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
#define PLAT_CPU_RELEASE_ADDR 0xffd12210 #define PLAT_CPU_RELEASE_ADDR 0xffd12210
@ -170,14 +171,12 @@
#define CRASH_CONSOLE_BASE PLAT_UART0_BASE #define CRASH_CONSOLE_BASE PLAT_UART0_BASE
#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE
#ifndef SIMICS_BUILD #if PLAT_SOCFPGA_EMULATOR
#define PLAT_BAUDRATE (115200)
#define PLAT_UART_CLOCK (100000000)
#else
#define PLAT_BAUDRATE (4800) #define PLAT_BAUDRATE (4800)
#define PLAT_UART_CLOCK (76800) #define PLAT_UART_CLOCK (76800)
#else
#define PLAT_BAUDRATE (115200)
#define PLAT_UART_CLOCK (100000000)
#endif #endif
/******************************************************************************* /*******************************************************************************

1
plat/intel/soc/n5x/platform.mk
View file

@ -49,5 +49,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1 BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0 BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1 MULTI_CONSOLE_API := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1 USE_COHERENT_MEM := 1

1
plat/intel/soc/stratix10/platform.mk
View file

@ -77,5 +77,4 @@ BL31_SOURCES += \
PROGRAMMABLE_RESET_ADDRESS := 0 PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1 BL2_AT_EL3 := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1 USE_COHERENT_MEM := 1