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uniphier: set PROGRAMMABLE_RESET_ADDRESS to disable warm boot mailbox
The warm boot mailbox code is compiled if PROGRAMMABLE_RESET_ADDRESS is disabled. The warm boot mailbox is useless for UniPhier SoC family because BL1 is not the first image. The UniPhier platform implements non-TF ROM, then BL1 works as a pseudo ROM, so it is never executed in the warm boot. The reset vector address is not actually programmable for UniPhier platform, but it should not hurt to enable PROGRAMMABLE_RESET_ADDRESS to disable the mailbox and remove pointless plat_get_my_entrypoint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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2 changed files with 8 additions and 23 deletions
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@ -1,15 +1,16 @@
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#
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# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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override COLD_BOOT_SINGLE_CPU := 1
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override ENABLE_PLAT_COMPAT := 0
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override LOAD_IMAGE_V2 := 1
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override USE_COHERENT_MEM := 1
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override USE_TBBR_DEFS := 1
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override ENABLE_SVE_FOR_NS := 0
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override COLD_BOOT_SINGLE_CPU := 1
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override ENABLE_PLAT_COMPAT := 0
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override LOAD_IMAGE_V2 := 1
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override PROGRAMMABLE_RESET_ADDRESS := 1
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override USE_COHERENT_MEM := 1
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override USE_TBBR_DEFS := 1
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override ENABLE_SVE_FOR_NS := 0
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# Cortex-A53 revision r0p4-51rel0
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# needed for LD20, unneeded for LD11, PXs3 (no ACE)
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@ -48,7 +49,6 @@ PLAT_BL_COMMON_SOURCES += drivers/console/aarch64/console.S \
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BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a72.S \
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$(PLAT_PATH)/uniphier_bl1_helpers.S \
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$(PLAT_PATH)/uniphier_bl1_setup.c \
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$(IO_SOURCES)
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl plat_get_my_entrypoint
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func plat_get_my_entrypoint
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mov x0, #0
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ret
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endfunc plat_get_my_entrypoint
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