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refactor(neoverse-rd): remove soc_css.mk from common makefile

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The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.

Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935
This commit is contained in:
Rohit Mathew 2023-12-31 18:26:15 +00:00 • committed by Rohit Mathew
parent a965d73f02
commit 8d6fb77a96
3 changed files with 20 additions and 23 deletions
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22
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h
View file

@ -339,19 +339,6 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
* ROS peripheral config
******************************************************************************/
#define SOC_CSS_NIC400_USB_EHCI U(0)
#define SOC_CSS_NIC400_TLX_MASTER U(1)
#define SOC_CSS_NIC400_USB_OHCI U(2)
#define SOC_CSS_NIC400_PL354_SMC U(3)
#define SOC_CSS_NIC400_APB4_BRIDGE U(4)
#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5)
#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12)
#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
/* SoC NIC-400 Global Programmers View (GPV) */
#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
/* Non-volatile counters */
#define SOC_TRUSTED_NVCTR_BASE NRD_ROS_PLATFORM_PERIPH_BASE + \
UL(0x00E70000)
@ -360,15 +347,6 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
#define NTFW_CTR_SIZE U(4)
/* Keys */
#define SOC_KEYS_BASE UL(0x0EE80000)
#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
#define TZ_PUB_KEY_HASH_SIZE U(32)
#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
#define HU_KEY_SIZE U(16)
#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
#define END_KEY_SIZE U(32)
/*******************************************************************************
* MMU config
******************************************************************************/

2
plat/arm/board/neoverse_rd/common/nrd-common.mk
View file

@ -42,6 +42,7 @@ ENT_GIC_SOURCES := ${GICV3_SOURCES} \
PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/arch/aarch64/nrd_helper.S
BL1_SOURCES += ${INTERCONNECT_SOURCES} \
${NRD_COMMON_BASE}/nrd_bl1_setup.c \
drivers/arm/sbsa/sbsa.c
BL2_SOURCES += ${NRD_COMMON_BASE}/nrd_image_load.c \
@ -77,5 +78,4 @@ USE_COHERENT_MEM := 0
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk
include plat/arm/soc/common/soc_css.mk
include plat/arm/board/common/board_common.mk

19
plat/arm/board/neoverse_rd/common/nrd_bl1_setup.c Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/soc/common/soc_css.h>
/*******************************************************************************
* Perform any BL1 specific platform actions.
******************************************************************************/
void soc_css_init_nic400(void)
{
}
void soc_css_init_pcie(void)
{
}