mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-20 19:44:23 +00:00
feat(mt8186): add common and MT8186 TRNG driver
Introduce a common RNG driver along with the specific driver for MT8186 platform. Change-Id: I9f4437b6a4b3e8564a035ff5abb681bcfe85bd1e Signed-off-by: Suyuan Su <suyuan.su@mediatek.com> Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
This commit is contained in:
Suyuan Su
Gavin Liu
parent
15d668c5a1
commit
8c1740e2f2
6 changed files with 243 additions and 1 deletions
153
plat/mediatek/drivers/rng/mt8186/rng_plat.c
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153
plat/mediatek/drivers/rng/mt8186/rng_plat.c
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@ -0,0 +1,153 @@
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/*
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* Copyright (c) 2024, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/smccc.h>
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#include <lib/spinlock.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <services/trng_svc.h>
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#include <smccc_helpers.h>
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#include <mtk_mmap_pool.h>
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#include <mtk_sip_svc.h>
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#include "rng_plat.h"
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static spinlock_t rng_lock;
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static int trng_wait(uint32_t reg, uint32_t expected_value)
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{
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uint64_t timeout = timeout_init_us(TRNG_TIME_OUT);
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uint32_t value = 0;
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do {
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value = mmio_read_32(reg);
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if ((value & expected_value) == expected_value)
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return 0;
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udelay(10);
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} while (!timeout_elapsed(timeout));
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return -ETIMEDOUT;
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}
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static int trng_write(uint32_t reg, uint32_t value,
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uint32_t read_reg, uint32_t expected_value)
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{
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int retry = MTK_TRNG_MAX_ROUND;
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uint32_t read_value = 0;
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do {
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mmio_write_32(reg, value);
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read_value = mmio_read_32(read_reg);
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if ((read_value & value) == expected_value)
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return 0;
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udelay(10);
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} while (--retry > 0);
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return -ETIMEDOUT;
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}
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static uint32_t trng_prng(uint32_t *rand)
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{
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int32_t ret = 0;
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uint32_t seed[4] = {0};
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if (rand == NULL)
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return MTK_SIP_E_INVALID_PARAM;
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/* ungate */
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ret = trng_write(TRNG_PDN_CLR, TRNG_PDN_VALUE, TRNG_PDN_STATUS, 0);
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if (ret) {
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ERROR("%s: ungate fail\n", __func__);
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return MTK_SIP_E_NOT_SUPPORTED;
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}
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/* read random data once and drop it */
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seed[0] = mmio_read_32(TRNG_DATA);
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/* enable von-neumann extractor */
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mmio_setbits_32(TRNG_CONF, TRNG_CONF_VON_EN);
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/* start */
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mmio_setbits_32(TRNG_CTRL, TRNG_CTRL_START);
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/* get seeds from trng */
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for (int i = 0; i < ARRAY_SIZE(seed); i++) {
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ret = trng_wait(TRNG_CTRL, TRNG_CTRL_RDY);
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if (ret) {
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ERROR("%s: trng NOT ready\n", __func__);
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return MTK_SIP_E_NOT_SUPPORTED;
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}
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seed[i] = mmio_read_32(TRNG_DATA);
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}
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/* stop */
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mmio_clrbits_32(TRNG_CTRL, TRNG_CTRL_START);
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/* gate */
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ret = trng_write(TRNG_PDN_SET, TRNG_PDN_VALUE, TRNG_PDN_STATUS, TRNG_PDN_VALUE);
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if (ret) {
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ERROR("%s: gate fail\n", __func__);
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return MTK_SIP_E_NOT_SUPPORTED;
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}
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for (int i = 0; i < ARRAY_SIZE(seed); i++)
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rand[i] = seed[i];
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return 0;
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}
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static uint32_t get_true_rnd(uint32_t *val, uint32_t num)
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{
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uint32_t rand[4] = {0};
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uint32_t ret;
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if (val == NULL || num > ARRAY_SIZE(rand))
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return MTK_SIP_E_INVALID_PARAM;
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spin_lock(&rng_lock);
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ret = trng_prng(rand);
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spin_unlock(&rng_lock);
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for (int i = 0; i < num; i++)
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val[i] = rand[i];
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return ret;
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}
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/*
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* plat_get_entropy - get 64-bit random number data which is used form
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* atf early stage
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* output - out: output 64-bit entropy combine with 2 32-bit random number
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*/
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bool plat_get_entropy(uint64_t *out)
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{
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uint32_t entropy_pool[2] = {0};
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uint32_t ret;
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assert(out);
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assert(!check_uptr_overflow((uintptr_t)out, sizeof(*out)));
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/* Get 2 32-bits entropy */
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ret = get_true_rnd(entropy_pool, ARRAY_SIZE(entropy_pool));
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if (ret)
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return false;
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/* Output 8 bytes entropy combine with 2 32-bit random number. */
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*out = ((uint64_t)entropy_pool[0] << 32) | entropy_pool[1];
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return true;
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}
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30
plat/mediatek/drivers/rng/mt8186/rng_plat.h
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30
plat/mediatek/drivers/rng/mt8186/rng_plat.h
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@ -0,0 +1,30 @@
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/*
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* Copyright (c) 2024, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RNG_PLAT_H
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#define RNG_PLAT_H
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#define TRNG_TIME_OUT 1000
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#define MTK_TRNG_MAX_ROUND 4
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/*******************************************************************************
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* TRNG related constants
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******************************************************************************/
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#define TRNG_BASE_SIZE 0x1000
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#define TRNG_CTRL (TRNG_BASE + 0x0000)
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#define TRNG_TIME (TRNG_BASE + 0x0004)
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#define TRNG_DATA (TRNG_BASE + 0x0008)
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#define TRNG_CONF (TRNG_BASE + 0x000C)
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#define TRNG_CTRL_RDY 0x80000000
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#define TRNG_CTRL_START 0x00000001
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#define TRNG_CONF_VON_EN 0x00000020
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#define TRNG_PDN_BASE_SIZE 0x1000
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#define TRNG_PDN_SET (INFRACFG_AO_BASE + 0x0088)
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#define TRNG_PDN_CLR (INFRACFG_AO_BASE + 0x008C)
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#define TRNG_PDN_STATUS (INFRACFG_AO_BASE + 0x0094)
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#define TRNG_PDN_VALUE 0x200
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#endif /* RNG_PLAT_H */
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29
plat/mediatek/drivers/rng/rng.c
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29
plat/mediatek/drivers/rng/rng.c
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@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2024, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <lib/smccc.h>
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#include <plat/common/plat_trng.h>
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#include <mtk_sip_svc.h>
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DEFINE_SVC_UUID2(_plat_trng_uuid,
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0xf6b2c8d9, 0x1abb, 0x4d83, 0xb2, 0x3f,
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0x5c, 0x51, 0xb6, 0xef, 0xfc, 0xaf
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);
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uuid_t plat_trng_uuid;
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void plat_entropy_setup(void)
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{
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uint64_t placeholder;
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plat_trng_uuid = _plat_trng_uuid;
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/* Initialise the entropy source and trigger RNG generation */
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plat_get_entropy(&placeholder);
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}
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17
plat/mediatek/drivers/rng/rules.mk
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17
plat/mediatek/drivers/rng/rules.mk
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@ -0,0 +1,17 @@
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#
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# Copyright (c) 2024, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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LOCAL_DIR := $(call GET_LOCAL_DIR)
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MODULE := rng
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PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
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PLAT_INCLUDES += -I${LOCAL_DIR}
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LOCAL_SRCS-y := ${LOCAL_DIR}/rng.c
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LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/rng_plat.c
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$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
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@ -76,6 +76,11 @@
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******************************************************************************/
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#define MSDC0_BASE (IO_PHYS + 0x01230000)
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/*******************************************************************************
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* TRNG related constants
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******************************************************************************/
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#define TRNG_BASE (IO_PHYS + 0x0020F000)
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/*******************************************************************************
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* GIC-600 & interrupt handling related constants
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******************************************************************************/
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
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# Copyright (c) 2021-2024, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -7,6 +7,9 @@
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MTK_PLAT := plat/mediatek
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MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
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# True Random Number Generator firmware Interface
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TRNG_SUPPORT := 1
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PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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-I${MTK_PLAT}/drivers/cirq/ \
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-I${MTK_PLAT}/drivers/gic600/ \
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@ -79,6 +82,11 @@ BL31_SOURCES += common/desc_image_load.c \
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${MTK_PLAT_SOC}/plat_sip_calls.c \
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${MTK_PLAT_SOC}/plat_topology.c
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ifeq (${TRNG_SUPPORT},1)
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BL31_SOURCES += ${MTK_PLAT}/drivers/rng/rng.c \
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${MTK_PLAT}/drivers/rng/${PLAT}/rng_plat.c
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endif
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# Build SPM drivers
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include ${MTK_PLAT_SOC}/drivers/spm/build.mk
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