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fix(stm32mp13-fdts): cosmetic fixes in PLL nodes
- remove spaces in DT properties. - rename pll3_vco_417_8Mhz into pll3_vco_417Mhz Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Change-Id: Iec3b9ef70dd3c70873263f4959bf6c03d26cbe7d
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2a4abe0b37
commit
8b826636a3
1 changed files with 18 additions and 18 deletions
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@ -223,20 +223,20 @@
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};
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};
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pll2_vco_1066Mhz: pll2-vco-1066Mhz {
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pll2_vco_1066Mhz: pll2-vco-1066Mhz {
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src = < CLK_PLL12_HSE >;
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src = <CLK_PLL12_HSE>;
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divmn = < 2 65 >;
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divmn = <2 65>;
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frac = < 0x1400 >;
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frac = <0x1400>;
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};
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};
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pll3_vco_417_8Mhz: pll3-vco-417_8Mhz {
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pll3_vco_417Mhz: pll3-vco-417Mhz {
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src = < CLK_PLL3_HSE >;
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src = <CLK_PLL3_HSE>;
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divmn = < 1 33 >;
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divmn = <1 33>;
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frac = < 0x1a04 >;
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frac = <0x1a04>;
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};
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};
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pll4_vco_600Mhz: pll4-vco-600Mhz {
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pll4_vco_600Mhz: pll4-vco-600Mhz {
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src = < CLK_PLL4_HSE >;
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src = <CLK_PLL4_HSE>;
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divmn = < 1 49 >;
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divmn = <1 49>;
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};
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};
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};
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};
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@ -258,11 +258,11 @@
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compatible = "st,stm32mp1-pll";
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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reg = <1>;
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st,pll = < &pll2_cfg1 >;
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st,pll = <&pll2_cfg1>;
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pll2_cfg1: pll2_cfg1 {
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pll2_cfg1: pll2_cfg1 {
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st,pll_vco = < &pll2_vco_1066Mhz >;
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st,pll_vco = <&pll2_vco_1066Mhz>;
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st,pll_div_pqr = < 1 1 0 >;
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st,pll_div_pqr = <1 1 0>;
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};
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};
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};
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};
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@ -271,11 +271,11 @@
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compatible = "st,stm32mp1-pll";
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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reg = <2>;
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st,pll = < &pll3_cfg1 >;
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st,pll = <&pll3_cfg1>;
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pll3_cfg1: pll3_cfg1 {
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pll3_cfg1: pll3_cfg1 {
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st,pll_vco = < &pll3_vco_417_8Mhz >;
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st,pll_vco = <&pll3_vco_417Mhz>;
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st,pll_div_pqr = < 1 16 1 >;
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st,pll_div_pqr = <1 16 1>;
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};
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};
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};
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};
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@ -284,11 +284,11 @@
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compatible = "st,stm32mp1-pll";
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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reg = <3>;
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st,pll = < &pll4_cfg1 >;
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st,pll = <&pll4_cfg1>;
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pll4_cfg1: pll4_cfg1 {
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pll4_cfg1: pll4_cfg1 {
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st,pll_vco = < &pll4_vco_600Mhz >;
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st,pll_vco = <&pll4_vco_600Mhz>;
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st,pll_div_pqr = < 11 59 5 >;
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st,pll_div_pqr = <11 59 5>;
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};
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};
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};
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};
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};
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};
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