From 842ba2f22196beab45a581517ad43a6cdbf61d9a Mon Sep 17 00:00:00 2001 From: Rakshit Goyal Date: Mon, 27 Jan 2025 11:42:06 +0000 Subject: [PATCH 1/8] fix(neoverse-rd): set correct SVE vector lengths Affected platforms: RD-N2, RD-V1, RD-V1-MC, RD-V3 and their configurations. Previously, the SVE vector lengths for these platforms were being taken from the default configuration. This commit updates their respective platform.mk files to specify the correct vector lengths. Signed-off-by: Rakshit Goyal Change-Id: I8919257e2cec5c0e819424ff44a623dc3ab1a368 --- plat/arm/board/neoverse_rd/platform/rdn2/platform.mk | 4 +++- plat/arm/board/neoverse_rd/platform/rdv1/platform.mk | 5 ++++- plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk | 5 ++++- plat/arm/board/neoverse_rd/platform/rdv3/platform.mk | 5 ++++- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk index c2dfba6e9..577694895 100644 --- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -113,6 +113,8 @@ override ENABLE_FEAT_AMU := 2 override ENABLE_FEAT_MTE2 := 2 override SPMD_SPM_AT_SEL2 := 0 +# FEAT_SVE related flags +override SVE_VECTOR_LEN := 128 # Enable the flag since RD-N2 has a system level cache NEOVERSE_Nx_EXTERNAL_LLC := 1 diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk index db8efbbe6..241133fcd 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -61,6 +61,9 @@ override CTX_INCLUDE_AARCH32_REGS := 0 override ENABLE_FEAT_AMU := 2 override SPMD_SPM_AT_SEL2 := 0 +# FEAT_SVE related flags +override SVE_VECTOR_LEN := 256 + ifneq ($(NRD_PLATFORM_VARIANT),0) $(error "NRD_PLATFORM_VARIANT for RD-V1 should always be 0, \ currently set to ${NRD_PLATFORM_VARIANT}.") diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk index 6d518d5c9..7af0bd85a 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -72,6 +72,9 @@ override CTX_INCLUDE_AARCH32_REGS := 0 override ENABLE_FEAT_AMU := 2 override SPMD_SPM_AT_SEL2 := 0 +# FEAT_SVE related flags +override SVE_VECTOR_LEN := 256 + ifneq ($(NRD_PLATFORM_VARIANT),0) $(error "NRD_PLATFORM_VARIANT for RD-V1-MC should always be 0, \ currently set to ${NRD_PLATFORM_VARIANT}.") diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk index f37d90383..b05b1f819 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -153,4 +153,7 @@ override ENABLE_FEAT_AMU := 2 override ENABLE_SVE_FOR_SWD := 1 override ENABLE_SVE_FOR_NS := 2 override ENABLE_FEAT_MTE2 := 2 + +# FEAT_SVE related flags +override SVE_VECTOR_LEN := 128 override CTX_INCLUDE_SVE_REGS := 1 From 82f46593de26d758457391d8b5036abcc533c7e3 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Wed, 27 Sep 2023 22:10:34 +0100 Subject: [PATCH 2/8] feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled Larger stack size is needed when S-EL2 SPMC is enabled. This is required because BL31 xlat map framework makes more nested calls when this feature is enabled. Signed-off-by: Nishant Sharma Signed-off-by: Rakshit Goyal Change-Id: Ib3f2abf38b576ba96402dab4ba995d8b648b4cc7 --- .../board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h index 8d6d1cb3c..aabfb91ff 100644 --- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h +++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h @@ -118,7 +118,7 @@ #elif defined(IMAGE_BL2U) # define PLATFORM_STACK_SIZE UL(0x400) #elif defined(IMAGE_BL31) -# if SPM_MM +# if SPM_MM || SPMD_SPM_AT_SEL2 # define PLATFORM_STACK_SIZE UL(0x500) # else # define PLATFORM_STACK_SIZE UL(0x400) From 4593b932396dca2ed945ab2c95c6cc6712c3eeeb Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 27 Jun 2024 20:38:34 +0100 Subject: [PATCH 3/8] feat(rdv3): introduce platform handler for Group0 interrupt This patch introduces a handler for RD-V3 variants to handle Group0 secure interrupts. Currently, it is empty but serves as a placeholder for future Group0 interrupt sources. Signed-off-by: Nishant Sharma Signed-off-by: Rakshit Goyal Change-Id: Ifa418094f6075a6cdc33e63eec1825103bbf6d68 --- .../board/neoverse_rd/platform/rdv3/rdv3_common.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c index dba83abef..3ef9681e1 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c +++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -198,3 +198,13 @@ int plat_rse_comms_init(void) /* Initialize the communication channel between AP and RSE */ return rse_comms_init(snd_base, rcv_base); } + +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + /* + * As of now, there are no sources of Group0 secure interrupt enabled + * for FVP. + */ + (void)intid; + return -1; +} From 6823f5f520e7dfcd0812bdf8d93deb8c770de5e8 Mon Sep 17 00:00:00 2001 From: Rohit Mathew Date: Tue, 2 Apr 2024 15:16:03 +0100 Subject: [PATCH 4/8] feat(rdv3): add carveout for BL32 image Add and map the carveout for loading Hafnium as BL32 image. Also define PLAT_ARM_SP_MAX_SIZE as 3 MB for secure partitions. Signed-off-by: Rohit Mathew Signed-off-by: Nishant Sharma Signed-off-by: Rakshit Goyal Change-Id: I2845eb6807a127c9f6b92de2dabc9a58d25bd4d4 --- .../common/include/nrd3/nrd_css_fw_def3.h | 10 +++++- .../common/include/nrd3/nrd_pas_def3.h | 13 +++++++- .../common/include/nrd3/nrd_plat_arm_def3.h | 33 +++++++++++++++++-- plat/arm/board/neoverse_rd/common/nrd_plat3.c | 5 ++- .../platform/rdv3/rdv3_bl2_setup.c | 5 ++- 5 files changed, 60 insertions(+), 6 deletions(-) diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h index 706b2017a..bbfbe0140 100644 --- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h +++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -111,6 +111,14 @@ ARM_REALM_SIZE, \ MT_MEMORY | MT_RW | MT_REALM) +#if SPD_spmd && SPMD_SPM_AT_SEL2 +#define NRD_CSS_SPM_CORE_REGION_MMAP \ + MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + #if RESET_TO_BL31 /******************************************************************************* * BL31 specific defines. diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h index 7d14e811d..914560cc0 100644 --- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h +++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -177,6 +177,9 @@ * --------------------------------------------------------------------- * 0x80000000 |2GB - |L1 GPT |NS |NS DRAM | * 0xF3FFFFFF |192MB | | | | + * --------------------------------------------------------------------| + * 0xF4000000 |9692KB |L1 GPT |SECURE |BL32 | + * 0xFB200000 | | | | | * --------------------------------------------------------------------- * 0x80000000 |26MB |L1 GPT |REALM |RMM | * 0x37FFFFFF | | | |TF-A SHARED | @@ -514,6 +517,14 @@ ARM_DRAM1_SIZE, \ GPT_GPI_NS) +#if SPD_spmd && SPMD_SPM_AT_SEL2 +#define NRD_PAS_BL32 \ + GPT_MAP_REGION_GRANULE( \ + PLAT_ARM_SPMC_BASE, \ + PLAT_ARM_SPMC_SIZE, \ + GPT_GPI_SECURE) +#endif + #define NRD_PAS_RMM \ GPT_MAP_REGION_GRANULE( \ ARM_REALM_BASE, \ diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h index aabfb91ff..f16a7c9a0 100644 --- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h +++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -608,9 +608,13 @@ * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM * - REALM DRAM: Reserved for Realm world if RME is enabled + * - BL32: Carveout for BL32 image if BL32 is present * * DRAM layout * +------------------+ + * | | + * | BL32 | + * +------------------+ * | REALM (RMM) | * | (32MB - 4KB) | * +------------------+ @@ -695,6 +699,14 @@ #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) +/******************************************************************************* + * S-EL2 SPMC region defines. + ******************************************************************************/ +/* BL32 (1500KB) + PLAT_ARM_SP_MAX_SIZE (3MB) + SP HEAP (5MB) */ +/* 9692KB */ +#define PLAT_ARM_SPMC_SIZE (UL(1500 * 1024) + UL(0x300000) + UL(0x500000)) +#define PLAT_ARM_SPMC_BASE (RMM_BASE - PLAT_ARM_SPMC_SIZE) + /******************************************************************************* * NRD_CSS_CARVEOUT_RESERVED region specific defines. ******************************************************************************/ @@ -705,11 +717,22 @@ #define NRD_CSS_CARVEOUT_RESERVED_SIZE (NRD_CSS_DRAM1_CARVEOUT_SIZE - \ (ARM_EL3_RMM_SHARED_SIZE + \ ARM_REALM_SIZE + \ - ARM_L1_GPT_SIZE)) + ARM_L1_GPT_SIZE + \ + PLAT_ARM_SPMC_SIZE)) #define NRD_CSS_CARVEOUT_RESERVED_END (NRD_CSS_CARVEOUT_RESERVED_BASE +\ NRD_CSS_CARVEOUT_RESERVED_SIZE - 1U) +/******************************************************************************* + * BL32 specific defines for EL3 runtime in AArch64 mode + ******************************************************************************/ + +#if SPD_spmd && SPMD_SPM_AT_SEL2 +# define BL32_BASE PLAT_ARM_SPMC_BASE +# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ + PLAT_ARM_SPMC_SIZE) +# endif + /******************************************************************************* * NS RAM specific defines specific defines. ******************************************************************************/ @@ -721,6 +744,12 @@ #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ ARM_NS_DRAM1_SIZE - 1U) +/******************************************************************************* + * Secure Partition specific defines. + ******************************************************************************/ + +#define PLAT_ARM_SP_MAX_SIZE U(0x300000) /* 3MB */ + /******************************************************************************* * MMU mapping ******************************************************************************/ diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c index 00f346ecd..5811bc071 100644 --- a/plat/arm/board/neoverse_rd/common/nrd_plat3.c +++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,6 +39,9 @@ const mmap_region_t plat_arm_mmap[] = { NRD_ROS_PLATFORM_PERIPH_MMAP, NRD_ROS_SYSTEM_PERIPH_MMAP, NRD_CSS_NS_DRAM1_MMAP, +#if SPD_spmd && SPMD_SPM_AT_SEL2 + NRD_CSS_SPM_CORE_REGION_MMAP, +#endif #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 NRD_CSS_BL1_RW_MMAP, #endif diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_setup.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_setup.c index 8dac8d3a5..1ee5f5347 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_setup.c +++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -59,6 +59,9 @@ static pas_region_t pas_regions[] = { NRD_PAS_SCP_MCP_RSE_SHARED_SRAM, NRD_PAS_GIC, NRD_PAS_NS_DRAM, +#if SPD_spmd && SPMD_SPM_AT_SEL2 + NRD_PAS_BL32, +#endif NRD_PAS_RMM, NRD_PAS_L1GPT, NRD_PAS_CMN, From eab1ed54bfb6038a0c1ada79de409a5506e4dae0 Mon Sep 17 00:00:00 2001 From: Rakshit Goyal Date: Mon, 29 Apr 2024 11:03:20 +0530 Subject: [PATCH 5/8] feat(arm): add a macro for SPMC manifest base address In RESET_TO_BL31, the SPMC manifest base address that is utilized by bl32_image_ep_info has to be statically defined as DT is not available. Common arm code sets this to the top of SRAM using macros but it can be different for some platforms. Hence, introduce the macro PLAT_ARM_SPMC_MANIFEST_BASE that could be re-defined by platform as per their use-case. Platforms that utilize arm_def.h would use the existing value from arm common code. Signed-off-by: Rakshit Goyal Change-Id: I4491749ad2b5794e06c9bd11ff61e2e64f21a948 --- include/plat/arm/common/arm_def.h | 17 ++++++++++++++++- plat/arm/common/arm_bl31_setup.c | 11 ++--------- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index ec5f90bf1..3ce6a91dd 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -753,6 +753,21 @@ MEASURED_BOOT # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ +#if RESET_TO_BL31 && defined(SPD_spmd) && defined(PLAT_ARM_SPMC_MANIFEST_BASE) +#define ARM_SPMC_MANIFEST_BASE PLAT_ARM_SPMC_MANIFEST_BASE +#else + +/* + * SPM expects SPM Core manifest base address in x0, which in !RESET_TO_BL31 + * case loaded after base of non shared SRAM(after 4KB offset of SRAM). But in + * RESET_TO_BL31 case all non shared SRAM is allocated to BL31, so to avoid + * overwriting of manifest keep it in the last page. + */ +#define ARM_SPMC_MANIFEST_BASE (ARM_TRUSTED_SRAM_BASE + \ + PLAT_ARM_TRUSTED_SRAM_SIZE -\ + PAGE_SIZE) +#endif + /******************************************************************************* * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. ******************************************************************************/ diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 478799512..ce1545f5e 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -210,14 +210,7 @@ void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_confi bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); #if defined(SPD_spmd) - /* SPM (hafnium in secure world) expects SPM Core manifest base address - * in x0, which in !RESET_TO_BL31 case loaded after base of non shared - * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non - * shared SRAM is allocated to BL31, so to avoid overwriting of manifest - * keep it in the last page. - */ - bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + - PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; + bl32_image_ep_info.args.arg0 = ARM_SPMC_MANIFEST_BASE; #endif # endif /* BL32_BASE */ From 12973bcc89eff3a4bb4953061d48e8805b3c6079 Mon Sep 17 00:00:00 2001 From: Rakshit Goyal Date: Wed, 5 Jun 2024 10:58:18 +0530 Subject: [PATCH 6/8] feat(rdv3): define SPMC manifest base address ARM_SPMC_MANIFEST_BASE defines the base address of the SPMC manifest used by BL32. In the non-RESET_TO_BL31 case, it is defined relative to the top of Trusted SRAM. However, for RESET_TO_BL31, the PLAT_ARM_SPMC_MANIFEST_BASE macro can be used to set it to a different location which is then used to populate ARM_SPMC_MANIFEST_BASE. As the RD-V3 platform and its variants have a different SRAM layout compared to that defined in arm_def.h, define the PLAT_ARM_SPMC_MANIFEST_BASE macro to an address suitable for this platform and its variants. Signed-off-by: Rakshit Goyal Change-Id: I36e1eb21ab3d1c68bddb52c62198fcdfc40d8993 --- .../neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h index f16a7c9a0..7fa2b775d 100644 --- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h +++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h @@ -731,6 +731,12 @@ # define BL32_BASE PLAT_ARM_SPMC_BASE # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ PLAT_ARM_SPMC_SIZE) + +#if RESET_TO_BL31 +# define PLAT_ARM_SPMC_MANIFEST_BASE UL(0x1F500) +# define ARM_SPMC_MANIFEST_BASE PLAT_ARM_SPMC_MANIFEST_BASE +#endif + # endif /******************************************************************************* From 4d9b8281f35256f7367a6b76b1259d9edbefe713 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 14 Sep 2023 09:14:03 +0100 Subject: [PATCH 7/8] feat(rdv3): add dts files to enable hafnium as BL32 On RD-V3 platform and variants, Hafnium is used as SPMC running at S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured as BL32 image. SP is loaded by SP load framework and configured by Hafnium. Add the dts files needed to enable load and configuration of hafnium and SP. Signed-off-by: Nishant Sharma Signed-off-by: Rohit Mathew Signed-off-by: Rakshit Goyal Change-Id: I7de72052323ff9106d7bedbaaf5ece3272e9a6cd --- fdts/rdv3-defs.dtsi | 37 ++++++++ .../platform/rdv3/fdts/rdv3_fw_config.dts | 9 +- .../rdv3/fdts/rdv3_spmc_sp_manifest.dts | 85 +++++++++++++++++++ .../platform/rdv3/fdts/rdv3_tb_fw_config.dts | 11 ++- .../neoverse_rd/platform/rdv3/platform.mk | 6 ++ 5 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 fdts/rdv3-defs.dtsi create mode 100644 plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts diff --git a/fdts/rdv3-defs.dtsi b/fdts/rdv3-defs.dtsi new file mode 100644 index 000000000..0ec4ccc60 --- /dev/null +++ b/fdts/rdv3-defs.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RD_V3_DEFS_DTSI +#define RD_V3_DEFS_DTSI + +#define CONCAT(x, y) x##y +#define CONC(x, y) CONCAT(x, y) + +#define ADR(n) \ + CPU##n:cpu@n##0000 { + +#define PRE \ + device_type = "cpu"; \ + compatible = "arm,armv8"; + +#define CPU_0 \ + CPU0:cpu@0 { \ + PRE \ + reg = <0x0 0x0>;\ + }; + +#define POST }; + +/* + * n - CPU number + */ +#define CPU(n) \ + ADR(n) \ + PRE \ + reg = <0x0 CONC(0x, CONC(n, 0000))>; \ + POST + +#endif /* RD_V3_DEFS_DTSI */ diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts index 62ba0fad2..7a904fec7 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts +++ b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,13 @@ id = ; }; + tos_fw-config { + load-address = <0x0 0x01f500>; + secondary-load-address = <0x0 0xF9200000>; + max-size = <0x1000>; + id = ; + }; + nt_fw-config { load-address = <0x0 0xF3000000>; max-size = <0x0100000>; diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts new file mode 100644 index 000000000..c9764e463 --- /dev/null +++ b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +#define AFF 00 + +#include "rdv3-defs.dtsi" + +/ { + compatible = "arm,ffa-core-manifest-1.0"; + #address-cells = <2>; + #size-cells = <2>; + + attribute { + spmc_id = <0x8000>; + maj_ver = <0x1>; + min_ver = <0x1>; + exec_state = <0x0>; + load_address = <0x0 0xfa889000>; + entrypoint = <0x0 0xfa889000>; + binary_size = <0x177000>; + }; + + hypervisor { + compatible = "hafnium,hafnium"; + vm1 { + is_ffa_partition; + debug_name = "stmm"; + load_address = <0xFAA00000>; + vcpu_count = <1>; + mem_size = <0x300000>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU_0 + + /* + * SPMC (Hafnium) requires secondary core nodes are declared + * in descending order. + */ +#if (NRD_PLATFORM_VARIANT != 1) + CPU(F) + CPU(E) + CPU(D) + CPU(C) + CPU(B) + CPU(A) + CPU(9) + CPU(8) +#endif + CPU(7) + CPU(6) + CPU(5) + CPU(4) + CPU(3) + CPU(2) + CPU(1) + }; + + memory@0 { + device_type = "memory"; + reg = /* Trusted DRAM for SPMC and SP */ + <0x0 0xfa889000 0x0 0x400000 + /* Trusted DRAM for SP Heap*/ + 0x0 0xfad00000 0x0 0x500000>; + }; + + memory@1 { + device_type = "ns-memory"; + /* DRAM for SP NS mappings*/ + reg = <0x0 0x80000000 0x0 0x78FE0000>; + }; + memory@2 { + device_type = "device-memory"; + reg = /* AP Memory Expansion 2 - Secure Flash*/ + <0x6 0x04000000 0x0 0x04000000>; + }; +}; diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts index a4c7c7286..77c47250d 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts +++ b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,4 +25,13 @@ mbedtls_heap_addr = <0x0 0x0>; mbedtls_heap_size = <0x0>; }; + + secure-partitions { + compatible = "arm,sp"; + stmm { + uuid = "eaba83d8-baaf-4eaf-8144-f7fdcbe544a7"; + load-address = <0xFAA00000>; + owner = "Plat"; + }; + }; }; diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk index b05b1f819..bae940cad 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk @@ -136,6 +136,12 @@ FDT_SOURCES += ${RDV3_BASE}/fdts/${PLAT}_fw_config.dts \ ${RDV3_BASE}/fdts/${PLAT}_tb_fw_config.dts \ ${RDV3_BASE}/fdts/${PLAT}_nt_fw_config.dts +ifeq (${SPMD_SPM_AT_SEL2}, 1) +BL32_CONFIG_DTS := ${RDV3_BASE}/fdts/${PLAT}_spmc_sp_manifest.dts +FDT_SOURCES += ${BL32_CONFIG_DTS} +TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${BL32_CONFIG_DTS})).dtb +endif + FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb From 37cc7fa539d9cfbbe1fefadb2346bc7415422fec Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 14 Sep 2023 09:31:37 +0100 Subject: [PATCH 8/8] feat(rdv3): enable the support to fetch dynamic config To enable the support to load Hafnium as BL32, BL31 needs firmware configuration info to get BL32 manifest load location. The load address of BL32 is passed via firmware config info. Add the support to get the address using fconf framework from dynamic config info. Signed-off-by: Nishant Sharma Signed-off-by: Rakshit Goyal Change-Id: I3a2a5706789ed290dc7f4a67e62e03751b930c02 --- .../board/neoverse_rd/common/nrd_bl31_setup.c | 19 ++++++++++- .../board/neoverse_rd/common/nrd_image_load.c | 32 +++++++++++++++++-- .../neoverse_rd/platform/rdv3/platform.mk | 7 ++++ 3 files changed, 55 insertions(+), 3 deletions(-) diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c index 39a86b19a..d3038ec4e 100644 --- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c +++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -155,6 +157,21 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, /* Initialize generic timer */ generic_delay_timer_init(); +#if SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 + INFO("BL31 FCONF: FW_CONFIG address = 0x%lx\n", (uintptr_t)arg1); + /* Initialize BL31's copy of the DTB registry because SPMD needs the + * TOS_FW_CONFIG's addresses to make a copy. + */ + fconf_populate("FW_CONFIG", arg1); + + /* arg1 is supposed to point to SOC_FW_CONFIG */ + const struct dyn_cfg_dtb_info_t *soc_fw_config_info; + + soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); + if (soc_fw_config_info != NULL) { + arg1 = soc_fw_config_info->config_addr; + } +#endif /* SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); } diff --git a/plat/arm/board/neoverse_rd/common/nrd_image_load.c b/plat/arm/board/neoverse_rd/common/nrd_image_load.c index 15d90beb0..ee1f2657b 100644 --- a/plat/arm/board/neoverse_rd/common/nrd_image_load.c +++ b/plat/arm/board/neoverse_rd/common/nrd_image_load.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include #include @@ -145,11 +147,37 @@ static int plat_nrd_append_config_node(void) ******************************************************************************/ bl_params_t *plat_get_next_bl_params(void) { + struct bl_params *arm_bl_params; int ret; ret = plat_nrd_append_config_node(); if (ret != 0) panic(); - return arm_get_next_bl_params(); + arm_bl_params = arm_get_next_bl_params(); + +#if !EL3_PAYLOAD_BASE + const struct dyn_cfg_dtb_info_t *fw_config_info; + bl_mem_params_node_t *param_node; + uintptr_t fw_config_base = 0UL; + + /* Get BL31 image node */ + param_node = get_bl_mem_params_node(BL31_IMAGE_ID); + assert(param_node != NULL); + + /* Get fw_config load address */ + fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); + assert(fw_config_info != NULL); + + fw_config_base = fw_config_info->config_addr; + assert(fw_config_base != 0UL); + + /* + * Get the entry point info of next executable image and override + * arg1 of entry point info with fw_config base address + */ + param_node->ep_info.args.arg1 = (uint64_t)fw_config_base; + +#endif + return arm_bl_params; } diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk index bae940cad..49b7cc316 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk @@ -127,6 +127,13 @@ ifeq (${NRD_PLATFORM_VARIANT}, 2) BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c endif +ifneq (${PLAT_RESET_TO_BL31}, 1) +ifeq ($(SPMD_SPM_AT_SEL2),1) +# Firmware Configuration Framework sources +BL31_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES} +endif +endif + # XLAT options for RD-V3 variants BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC