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Merge "fix(cpus): workaround for Cortex-A715 erratum 2728106" into integration
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commit
8acdb13a9a
3 changed files with 29 additions and 0 deletions
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@ -916,6 +916,10 @@ For Cortex-A715, the following errata build flags are defined :
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Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
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It is fixed in r1p1.
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- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to
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Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0
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and r1p1. It is fixed in r1p2.
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For Cortex-A720, the following errata build flags are defined :
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- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to
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@ -94,6 +94,27 @@ workaround_reset_end cortex_a715, ERRATUM(2561034)
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check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106
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mov x0, #3
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msr CORTEX_A715_CPUPSELR_EL3, x0
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isb
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ldr x0, =0xd503339f
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msr CORTEX_A715_CPUPOR_EL3, x0
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ldr x0, =0xfffff3ff
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msr CORTEX_A715_CPUPMR_EL3, x0
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mov x0, #1
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orr x0, x0, #(3<<4)
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orr x0, x0, #(0xf<<6)
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orr x0, x0, #(1<<13)
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orr x0, x0, #(1<<20)
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orr x0, x0, #(1<<22)
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orr x0, x0, #(1<<31)
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orr x0, x0, #(1<<50)
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msr CORTEX_A715_CPUPCR_EL3, x0
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workaround_reset_end cortex_a715, ERRATUM(2728106)
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check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1)
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workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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@ -940,6 +940,10 @@ CPU_FLAG_LIST += ERRATA_A715_2429384
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# only to revision r1p0. It is fixed in r1p1.
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CPU_FLAG_LIST += ERRATA_A715_2561034
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# Flag to apply erratum 2728106 workaround during reset. This erratum applies
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# only to revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
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CPU_FLAG_LIST += ERRATA_A715_2728106
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# Flag to apply erratum 2926083 workaround during reset. This erratum applies
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# to revisions r0p0 and r0p1. It is fixed in r0p2.
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CPU_FLAG_LIST += ERRATA_A720_2926083
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