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fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1. The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to invalidate the hardware prefetcher state trained from any EL. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
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@ -413,6 +413,10 @@ For Cortex-A710, the following errata build flags are defined :
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Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
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of the CPU and is fixed in r2p1.
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- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
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Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
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of the CPU and is fixed in r2p1.
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For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
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@ -33,6 +33,7 @@
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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@ -245,6 +245,36 @@ func check_errata_2267065
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b cpu_rev_var_ls
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endfunc check_errata_2267065
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/* ---------------------------------------------------------------
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* Errata Workaround for Cortex-A710 Erratum 2136059.
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* This applies to revision r0p0, r1p0 and r2p0.
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* It is fixed in r2p1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------
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*/
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func errata_a710_2136059_wa
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/* Compare x0 against revision r2p0 */
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mov x17, x30
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bl check_errata_2136059
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cbz x0, 1f
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/* Apply the workaround */
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mrs x1, CORTEX_A710_CPUACTLR5_EL1
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orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
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msr CORTEX_A710_CPUACTLR5_EL1, x1
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1:
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ret x17
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endfunc errata_a710_2136059_wa
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func check_errata_2136059
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/* Applies to r0p0, r1p0 and r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2136059
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -282,6 +312,7 @@ func cortex_a710_errata_report
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report_errata ERRATA_A710_2083908, cortex_a710, 2083908
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report_errata ERRATA_A710_2058056, cortex_a710, 2058056
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report_errata ERRATA_A710_2267065, cortex_a710, 2267065
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report_errata ERRATA_A710_2136059, cortex_a710, 2136059
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ldp x8, x30, [sp], #16
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ret
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@ -332,6 +363,11 @@ func cortex_a710_reset_func
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bl errata_a710_2267065_wa
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#endif
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#if ERRATA_A710_2136059
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mov x0, x18
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bl errata_a710_2136059_wa
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#endif
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isb
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ret x19
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endfunc cortex_a710_reset_func
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@ -499,6 +499,10 @@ ERRATA_A710_2017096 ?=0
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# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
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ERRATA_A710_2267065 ?=0
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# Flag to apply erratum 2136059 workaround during reset. This erratum applies
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# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
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ERRATA_A710_2136059 ?=0
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# Flag to apply erratum 2002765 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
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ERRATA_X2_2002765 ?=0
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@ -955,6 +959,10 @@ $(eval $(call add_define,ERRATA_A710_2017096))
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$(eval $(call assert_boolean,ERRATA_A710_2267065))
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$(eval $(call add_define,ERRATA_A710_2267065))
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# Process ERRATA_A710_2136059 flag
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$(eval $(call assert_boolean,ERRATA_A710_2136059))
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$(eval $(call add_define,ERRATA_A710_2136059))
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# Process ERRATA_X2_2002765 flag
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$(eval $(call assert_boolean,ERRATA_X2_2002765))
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$(eval $(call add_define,ERRATA_X2_2002765))
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