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fix(zynqmp): typecast expressions to match data type

Browse source 
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I847af07f5e4f139384c1ed50bee765b892a6e9cd
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
Maheedhar Bollapalli 2024-04-23 16:28:04 +05:30
parent 1877bf2ce1
commit 895e8029aa
8 changed files with 64 additions and 73 deletions
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10
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View file

@ -270,7 +270,7 @@ static char *zynqmp_get_silicon_idcode_name(void)
return zynqmp_devices[i].name; return zynqmp_devices[i].name;
} }
len = strlen(zynqmp_devices[i].name) - 2; len = strlen(zynqmp_devices[i].name) - 2U;
for (j = 0; j < strlen(name); j++) { for (j = 0; j < strlen(name); j++) {
zynqmp_devices[i].name[len] = name[j]; zynqmp_devices[i].name[len] = name[j];
len++; len++;
@ -327,7 +327,7 @@ int32_t plat_get_soc_version(void)
uint32_t chip_id = zynqmp_get_silicon_ver(); uint32_t chip_id = zynqmp_get_silicon_ver();
uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_XILINX_BKID, JEDEC_XILINX_MFID); uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_XILINX_BKID, JEDEC_XILINX_MFID);
return (int32_t)(manfid | (chip_id & 0xFFFF)); return (int32_t)(manfid | (chip_id & 0xFFFFU));
} }
int32_t plat_get_soc_revision(void) int32_t plat_get_soc_revision(void)
@ -366,7 +366,7 @@ static void zynqmp_print_platform_name(void)
VERBOSE("TF-A running on %s/%s at 0x%x\n", VERBOSE("TF-A running on %s/%s at 0x%x\n",
zynqmp_print_silicon_idcode(), label, BL31_BASE); zynqmp_print_silicon_idcode(), label, BL31_BASE);
VERBOSE("TF-A running on v%d/RTL%d.%d\n", VERBOSE("TF-A running on v%d/RTL%d.%d\n",
zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf); zynqmp_get_ps_ver(), (rtl & 0xf0U) >> 4, rtl & 0xfU);
} }
#else #else
static inline void zynqmp_print_platform_name(void) { } static inline void zynqmp_print_platform_name(void) { }
@ -375,7 +375,7 @@ static inline void zynqmp_print_platform_name(void) { }
uint32_t zynqmp_get_bootmode(void) uint32_t zynqmp_get_bootmode(void)
{ {
uint32_t r; uint32_t r;
unsigned int ret; enum pm_ret_status ret;
ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r); ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
@ -411,6 +411,6 @@ uint32_t plat_get_syscnt_freq2(void)
if (ver == ZYNQMP_CSU_VERSION_QEMU) { if (ver == ZYNQMP_CSU_VERSION_QEMU) {
return 65000000; return 65000000;
} else { } else {
return mmio_read_32(IOU_SCNTRS_BASEFREQ); return mmio_read_32((uint64_t)IOU_SCNTRS_BASEFREQ);
} }
} }

6
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View file

@ -96,7 +96,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); tfa_handoff_addr = (uint64_t)mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
bl31_set_default_config(); bl31_set_default_config();
@ -109,10 +109,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
panic(); panic();
} }
} }
if (bl32_image_ep_info.pc != 0) { if (bl32_image_ep_info.pc != 0U) {
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
} }
if (bl33_image_ep_info.pc != 0) { if (bl33_image_ep_info.pc != 0U) {
NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
} }

79
plat/xilinx/zynqmp/include/zynqmp_def.h
View file

@ -60,9 +60,9 @@
/* CRL registers and bitfields */ /* CRL registers and bitfields */
#define CRL_APB_BASE U(0xFF5E0000) #define CRL_APB_BASE U(0xFF5E0000)
#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + U(0x200))
#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) #define CRL_APB_RESET_CTRL (CRL_APB_BASE + U(0x218))
#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + U(0x23C))
#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250))
#define CRL_APB_CLK_BASE U(0xFF5E0020) #define CRL_APB_CLK_BASE U(0xFF5E0020)
@ -75,18 +75,15 @@
#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0)
#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9)
#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1)
#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \
CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
#define ZYNQMP_BOOTMODE_JTAG U(0) #define ZYNQMP_BOOTMODE_JTAG U(0)
#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | CRL_APB_BOOT_DRIVE_PIN_1)
CRL_APB_BOOT_DRIVE_PIN_1)
#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
/* system counter registers and bitfields */ /* system counter registers and bitfields */
#define IOU_SCNTRS_BASE U(0xFF260000) #define IOU_SCNTRS_BASE U(0xFF260000)
#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + U(0x20))
/* APU registers and bitfields */ /* APU registers and bitfields */
#define APU_BASE U(0xFD5C0000) #define APU_BASE U(0xFD5C0000)
@ -104,11 +101,11 @@
/* PMU registers and bitfields */ /* PMU registers and bitfields */
#define PMU_GLOBAL_BASE U(0xFFD80000) #define PMU_GLOBAL_BASE U(0xFFD80000)
#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + U(0x48))
#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + U(0x110))
#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + U(0x118))
#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + U(0x11c))
#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + U(0x120))
#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
@ -191,10 +188,10 @@
#define UART_BAUDRATE 115200 #define UART_BAUDRATE 115200
/* Silicon version detection */ /* Silicon version detection */
#define ZYNQMP_SILICON_VER_MASK 0xF000 #define ZYNQMP_SILICON_VER_MASK U(0xF000)
#define ZYNQMP_SILICON_VER_SHIFT 12 #define ZYNQMP_SILICON_VER_SHIFT 12
#define ZYNQMP_CSU_VERSION_SILICON 0 #define ZYNQMP_CSU_VERSION_SILICON 0
#define ZYNQMP_CSU_VERSION_QEMU 3 #define ZYNQMP_CSU_VERSION_QEMU U(3)
#define ZYNQMP_RTL_VER_MASK 0xFF0U #define ZYNQMP_RTL_VER_MASK 0xFF0U
#define ZYNQMP_RTL_VER_SHIFT 4 #define ZYNQMP_RTL_VER_SHIFT 4
@ -203,38 +200,32 @@
#define ZYNQMP_PS_VER_SHIFT 0 #define ZYNQMP_PS_VER_SHIFT 0
#define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000)
#define ZYNQMP_CSU_IDCODE_OFFSET 0x40U #define ZYNQMP_CSU_IDCODE_OFFSET U(0x40)
#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT U(0)
#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (U(0xFFF) << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) #define ZYNQMP_CSU_IDCODE_XILINX_ID U(0x093)
#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U #define ZYNQMP_CSU_IDCODE_SVD_SHIFT U(12)
#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
ZYNQMP_CSU_IDCODE_SVD_SHIFT) #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT U(15)
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (U(0xF) << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT U(19)
ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (U(0x3) << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT U(21)
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (U(0x7F) << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) #define ZYNQMP_CSU_IDCODE_FAMILY U(0x23)
#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U
#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \
ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT U(28)
#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ #define ZYNQMP_CSU_IDCODE_REVISION_MASK (U(0xF) << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
ZYNQMP_CSU_IDCODE_REVISION_SHIFT) #define ZYNQMP_CSU_IDCODE_REVISION U(0)
#define ZYNQMP_CSU_IDCODE_REVISION 0U
#define ZYNQMP_CSU_VERSION_OFFSET 0x44U #define ZYNQMP_CSU_VERSION_OFFSET U(0x44)
/* Efuse */ /* Efuse */
#define EFUSE_BASEADDR U(0xFFCC0000) #define EFUSE_BASEADDR U(0xFFCC0000)
#define EFUSE_IPDISABLE_OFFSET 0x1018 #define EFUSE_IPDISABLE_OFFSET 0x1018
#define EFUSE_IPDISABLE_VERSION 0x1FFU #define EFUSE_IPDISABLE_VERSION U(0x1FF)
#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20
/* Access control register defines */ /* Access control register defines */
@ -356,11 +347,11 @@
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
/* Global general storage register base address */ /* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U) #define GGS_BASEADDR U(0xFFD80030)
#define GGS_NUM_REGS U(4) #define GGS_NUM_REGS U(4)
/* Persistent global general storage register base address */ /* Persistent global general storage register base address */
#define PGGS_BASEADDR (0xFFD80050U) #define PGGS_BASEADDR U(0xFFD80050)
#define PGGS_NUM_REGS U(4) #define PGGS_NUM_REGS U(4)
/* PMU GGS4 register 4 is used for warm restart boot health status */ /* PMU GGS4 register 4 is used for warm restart boot health status */
@ -369,7 +360,7 @@
#define PM_BOOT_HEALTH_STATUS_MASK U(0x01) #define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
/* WDT restart scope shift and mask */ /* WDT restart scope shift and mask */
#define RESTART_SCOPE_SHIFT (3) #define RESTART_SCOPE_SHIFT (3)
#define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) #define RESTART_SCOPE_MASK (U(0x3) << RESTART_SCOPE_SHIFT)
/* AFI registers */ /* AFI registers */
#define AFIFM6_WRCTRL U(13) #define AFIFM6_WRCTRL U(13)

2
plat/xilinx/zynqmp/plat_psci.c
View file

@ -32,7 +32,7 @@ static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
static int32_t zynqmp_pwr_domain_on(u_register_t mpidr) static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
{ {
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
const struct pm_proc *proc; const struct pm_proc *proc;
uint32_t buff[3]; uint32_t buff[3];
enum pm_ret_status ret; enum pm_ret_status ret;

10
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View file

@ -2455,15 +2455,15 @@ enum pm_ret_status pm_api_clock_get_num_clocks(uint32_t *nclocks)
*/ */
void pm_api_clock_get_name(uint32_t clock_id, char *name) void pm_api_clock_get_name(uint32_t clock_id, char *name)
{ {
if (clock_id == CLK_MAX) { if (clock_id == (uint32_t)CLK_MAX) {
(void)memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ? (void)memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ?
CLK_NAME_LEN : sizeof(END_OF_CLK))); CLK_NAME_LEN : sizeof(END_OF_CLK)));
} else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) { } else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
(void)memset(name, 0, CLK_NAME_LEN); (void)memset(name, 0, CLK_NAME_LEN);
} else if (clock_id < CLK_MAX_OUTPUT_CLK) { } else if (clock_id < (uint32_t)CLK_MAX_OUTPUT_CLK) {
(void)memcpy(name, clocks[clock_id].name, CLK_NAME_LEN); (void)memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
} else { } else {
(void)memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name, (void)memcpy(name, ext_clocks[clock_id - (uint32_t)CLK_MAX_OUTPUT_CLK].name,
CLK_NAME_LEN); CLK_NAME_LEN);
} }
} }
@ -2646,7 +2646,7 @@ enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id,
enum pm_ret_status pm_api_clock_get_attributes(uint32_t clock_id, enum pm_ret_status pm_api_clock_get_attributes(uint32_t clock_id,
uint32_t *attr) uint32_t *attr)
{ {
if (clock_id >= CLK_MAX) { if (clock_id >= (uint32_t)CLK_MAX) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
@ -3055,7 +3055,7 @@ uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id)
uint32_t i; uint32_t i;
const struct pm_clock_node *nodes; const struct pm_clock_node *nodes;
if (clock_id >= CLK_MAX_OUTPUT_CLK) { if (clock_id >= (uint32_t)CLK_MAX_OUTPUT_CLK) {
return 0; return 0;
} }

8
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
View file

@ -1991,7 +1991,7 @@ enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs)
enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid, enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
uint32_t *ngroups) uint32_t *ngroups)
{ {
if (fid >= MAX_FUNCTION) { if (fid >= (uint32_t)MAX_FUNCTION) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
@ -2011,7 +2011,7 @@ enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
*/ */
void pm_api_pinctrl_get_function_name(uint32_t fid, char *name) void pm_api_pinctrl_get_function_name(uint32_t fid, char *name)
{ {
if (fid >= MAX_FUNCTION) { if (fid >= (uint32_t)MAX_FUNCTION) {
(void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); (void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
} else { } else {
(void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); (void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
@ -2045,7 +2045,7 @@ enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid,
uint16_t end_of_grp_offset; uint16_t end_of_grp_offset;
uint16_t i; uint16_t i;
if (fid >= MAX_FUNCTION) { if (fid >= (uint32_t)MAX_FUNCTION) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
@ -2090,7 +2090,7 @@ enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin,
uint32_t i; uint32_t i;
const uint16_t *grps; const uint16_t *grps;
if (pin >= MAX_PIN) { if (pin >= (uint32_t)MAX_PIN) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }

20
plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
View file

@ -343,7 +343,7 @@ enum pm_ret_status pm_req_wakeup(enum pm_node_id target,
/* encode set Address into 1st bit of address */ /* encode set Address into 1st bit of address */
encoded_address = address; encoded_address = address;
encoded_address |= !!set_address; encoded_address |= (uint32_t)!!set_address;
/* Send request to the PMU to perform the wake of the PU */ /* Send request to the PMU to perform the wake of the PU */
PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address, PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address,
@ -440,7 +440,7 @@ enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype)
{ {
uint32_t payload[PAYLOAD_ARG_CNT]; uint32_t payload[PAYLOAD_ARG_CNT];
if (type == PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY) { if (type == (uint32_t)PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY) {
/* Setting scope for subsequent PSCI reboot or shutdown */ /* Setting scope for subsequent PSCI reboot or shutdown */
pm_shutdown_scope = subtype; pm_shutdown_scope = subtype;
return PM_RET_SUCCESS; return PM_RET_SUCCESS;
@ -780,7 +780,7 @@ enum pm_ret_status check_api_dependency(uint8_t id)
ret = fw_api_version(api_dep_table[i].api_id, ret = fw_api_version(api_dep_table[i].api_id,
&version_type, 1); &version_type, 1);
if (ret != PM_RET_SUCCESS) { if (ret != (uint32_t)PM_RET_SUCCESS) {
return ret; return ret;
} }
@ -898,7 +898,7 @@ static enum pm_ret_status feature_check_partial(uint32_t api_id,
case PM_REGISTER_ACCESS: case PM_REGISTER_ACCESS:
case PM_FEATURE_CHECK: case PM_FEATURE_CHECK:
status = check_api_dependency(api_id); status = check_api_dependency(api_id);
if (status != PM_RET_SUCCESS) { if (status != (uint32_t)PM_RET_SUCCESS) {
return status; return status;
} }
return get_tfa_version_for_partial_apis(api_id, version); return get_tfa_version_for_partial_apis(api_id, version);
@ -925,13 +925,13 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version,
/* Get API version implemented in TF-A */ /* Get API version implemented in TF-A */
status = feature_check_tfa(api_id, version, bit_mask); status = feature_check_tfa(api_id, version, bit_mask);
if (status != PM_RET_ERROR_NO_FEATURE) { if (status != (uint32_t)PM_RET_ERROR_NO_FEATURE) {
return status; return status;
} }
/* Get API version implemented by firmware and TF-A both */ /* Get API version implemented by firmware and TF-A both */
status = feature_check_partial(api_id, version); status = feature_check_partial(api_id, version);
if (status != PM_RET_ERROR_NO_FEATURE) { if (status != (uint32_t)PM_RET_ERROR_NO_FEATURE) {
return status; return status;
} }
@ -940,20 +940,20 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version,
/* IOCTL call may return failure whose ID is not implemented in /* IOCTL call may return failure whose ID is not implemented in
* firmware but implemented in TF-A * firmware but implemented in TF-A
*/ */
if ((api_id != PM_IOCTL) && (status != PM_RET_SUCCESS)) { if ((api_id != (uint32_t)PM_IOCTL) && (status != PM_RET_SUCCESS)) {
return status; return status;
} }
*version = ret_payload[0]; *version = ret_payload[0];
/* Update IOCTL bit mask which are implemented in TF-A */ /* Update IOCTL bit mask which are implemented in TF-A */
if ((api_id == PM_IOCTL) || (api_id == PM_GET_OP_CHARACTERISTIC)) { if ((api_id == (uint32_t)PM_IOCTL) || (api_id == (uint32_t)PM_GET_OP_CHARACTERISTIC)) {
if (len < 2) { if (len < 2U) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
bit_mask[0] = ret_payload[1]; bit_mask[0] = ret_payload[1];
bit_mask[1] = ret_payload[2]; bit_mask[1] = ret_payload[2];
if (api_id == PM_IOCTL) { if (api_id == (uint32_t)PM_IOCTL) {
/* Get IOCTL's implemented by TF-A */ /* Get IOCTL's implemented by TF-A */
status = tfa_ioctl_bitmask(bit_mask); status = tfa_ioctl_bitmask(bit_mask);
} }

2
plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
View file

@ -354,7 +354,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
SMC_RET1(handle, (uint64_t)ret); SMC_RET1(handle, (uint64_t)ret);
case PM_GET_API_VERSION: case PM_GET_API_VERSION:
if (ipi_irq_flag == 0U) { if ((uint32_t)ipi_irq_flag == 0U) {
/* /*
* Enable IPI IRQ * Enable IPI IRQ
* assume the rich OS is OK to handle callback IRQs now. * assume the rich OS is OK to handle callback IRQs now.