mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
refactor(fvp_r): remove unused files and clean up makefiles
This patch removes files that are not used by TF-R as well as removes unused generic files from the TF-R makefile. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Idb15ac295dc77fd38735bf2844efdb73e6f7c89b
This commit is contained in:
johpow01
Gary Morrison
parent
3deb060015
commit
88c227374c
14 changed files with 110 additions and 459 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -82,10 +82,6 @@
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* Initialise MDCR_EL2, setting all fields rather than relying on
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* hw. Some fields are architecturally UNKNOWN on reset.
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*
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* MDCR_EL2.SDD: Set to one to disable AArch64 Secure self-hosted
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* debug. Debug exceptions, other than Breakpoint Instruction
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* exceptions, are disabled from all ELs in Secure state.
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*
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* MDCR_EL2.TDOSA: Set to zero so that EL2 and EL2 System register
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* access to the powerdown debug registers do not trap to EL2.
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*
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@ -97,17 +93,7 @@
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* register accesses to all Performance Monitors registers do not trap
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* to EL2.
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*
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* MDCR_EL2.SCCD: Set to one so that cycle counting by PMCCNTR_EL0
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* is prohibited in Secure state. This bit is RES0 in versions of the
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* architecture with FEAT_PMUv3p5 not implemented, setting it to 1
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* doesn't have any effect on them.
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*
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* MDCR_EL2.MCCD: Set to one so that cycle counting by PMCCNTR_EL0
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* is prohibited in EL2. This bit is RES0 in versions of the
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* architecture with FEAT_PMUv3p7 not implemented, setting it to 1
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* doesn't have any effect on them.
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*
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* MDCR_EL2.SPME: Set to zero so that event counting by the program-
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* MDCR_EL2.HPMD: Set to zero so that event counting by the program-
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* mable counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If
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* ARMv8.2 Debug is not implemented this bit does not have any effect
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* on the counters unless there is support for the implementation
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@ -115,9 +101,9 @@
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* ExternalSecureNoninvasiveDebugEnabled().
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, ((MDCR_EL2_RESET_VAL | MDCR_SDD_BIT | \
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MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \
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MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \
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mov_imm x0, ((MDCR_EL2_RESET_VAL | \
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MDCR_SPD32(MDCR_SPD32_DISABLE)) \
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& ~(MDCR_EL2_HPMD | MDCR_TDOSA_BIT | \
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MDCR_TDA_BIT | MDCR_TPM_BIT))
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msr mdcr_el2, x0
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@ -126,17 +112,6 @@
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* Initialise PMCR_EL0 setting all fields rather than relying
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* on hw. Some fields are architecturally UNKNOWN on reset.
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*
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* PMCR_EL0.LP: Set to one so that event counter overflow, that
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* is recorded in PMOVSCLR_EL0[0-30], occurs on the increment
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* that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU
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* is implemented. This bit is RES0 in versions of the architecture
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* earlier than ARMv8.5, setting it to 1 doesn't have any effect
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* on them.
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*
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* PMCR_EL0.LC: Set to one so that cycle counter overflow, that
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* is recorded in PMOVSCLR_EL0[31], occurs on the increment
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* that changes PMCCNTR_EL0[63] from 1 to 0.
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*
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* PMCR_EL0.DP: Set to one so that the cycle counter,
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* PMCCNTR_EL0 does not count when event counting is prohibited.
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*
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@ -146,8 +121,7 @@
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* counts on every clock cycle.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \
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PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \
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mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_DP_BIT) & \
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~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
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msr pmcr_el0, x0
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@ -22,13 +22,13 @@
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#warning "xlat_mpu library is currently experimental and its API may change in future."
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#if LOG_LEVEL < LOG_LEVEL_VERBOSE
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void xlat_mmap_print(__unused const mmap_region_t *mmap)
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{
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/* Empty */
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}
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#if LOG_LEVEL < LOG_LEVEL_VERBOSE
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void xlat_tables_print(__unused xlat_ctx_t *ctx)
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{
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/* Empty */
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@ -36,36 +36,48 @@ void xlat_tables_print(__unused xlat_ctx_t *ctx)
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#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
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static const char *invalid_descriptors_ommited =
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"%s(%d invalid descriptors omitted)\n";
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void xlat_tables_print(xlat_ctx_t *ctx)
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static void xlat_tables_print_internal(__unused xlat_ctx_t *ctx)
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{
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const char *xlat_regime_str;
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int used_page_tables;
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int region_to_use = 0;
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uintptr_t region_base;
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size_t region_size;
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uint64_t prenr_el2_value = 0U;
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if (ctx->xlat_regime == EL1_EL0_REGIME) {
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xlat_regime_str = "1&0";
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} else if (ctx->xlat_regime == EL2_REGIME) {
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xlat_regime_str = "2";
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} else {
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assert(ctx->xlat_regime == EL3_REGIME);
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xlat_regime_str = "3";
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/* If no EL3 and EL3 tables generated, then need to know. */
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/*
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* Keep track of how many invalid descriptors are counted in a row.
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* Whenever multiple invalid descriptors are found, only the first one
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* is printed, and a line is added to inform about how many descriptors
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* have been omitted.
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*/
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/*
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* TODO: Remove this WARN() and comment when these API calls are more
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* completely implemented and tested!
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*/
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WARN("%s in this early version of xlat_mpu library may not produce reliable results!",
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__func__);
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/*
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* Sequence through all regions and print those in-use (PRENR has an
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* enable bit for each MPU region, 1 for in-use or 0 for unused):
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*/
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prenr_el2_value = read_prenr_el2();
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for (region_to_use = 0; region_to_use < N_MPU_REGIONS;
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region_to_use++) {
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if (((prenr_el2_value >> region_to_use) & 1U) == 0U) {
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continue;
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}
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region_base = read_prbar_el2() & PRBAR_PRLAR_ADDR_MASK;
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region_size = read_prlar_el2() & PRBAR_PRLAR_ADDR_MASK;
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printf("Address: 0x%llx, size: 0x%llx ",
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(long long) region_base,
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(long long) region_size);
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}
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VERBOSE("Translation tables state:\n");
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VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str);
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VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address);
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VERBOSE(" Max allowed VA: 0x%lx\n", ctx->va_max_address);
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VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa);
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VERBOSE(" Max mapped VA: 0x%lx\n", ctx->max_va);
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}
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VERBOSE(" Initial lookup level: %u\n", ctx->base_level);
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VERBOSE(" Entries @initial lookup level: %u\n",
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ctx->base_table_entries);
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xlat_tables_print_internal(ctx, 0U, ctx->base_table,
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ctx->base_table_entries, ctx->base_level);
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void xlat_tables_print(__unused xlat_ctx_t *ctx)
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{
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xlat_tables_print_internal(ctx);
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}
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#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
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@ -1,91 +0,0 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include "../../../../bl1/bl1_private.h"
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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void cm_prepare_el2_exit(void);
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/* Following contains the cpu context pointers. */
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static void *bl1_cpu_context_ptr[2];
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void *cm_get_context(uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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return bl1_cpu_context_ptr[security_state];
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}
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void cm_set_context(void *context, uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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bl1_cpu_context_ptr[security_state] = context;
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}
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/*******************************************************************************
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* This function prepares the context for Secure/Normal world images.
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* Normal world images are transitioned to EL2(if supported) else EL1.
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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/*
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* Following array will be used for context management.
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* There are 2 instances, for the Secure and Non-Secure contexts.
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*/
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static cpu_context_t bl1_cpu_context[2];
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unsigned int security_state, mode = MODE_EL1;
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image_desc_t *desc;
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entry_point_info_t *next_bl_ep;
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#if CTX_INCLUDE_AARCH32_REGS
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/*
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* Ensure that the build flag to save AArch32 system registers in CPU
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* context is not set for AArch64-only platforms.
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*/
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if (el_implemented(1) == EL_IMPL_A64ONLY) {
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ERROR("EL1 supports AArch64-only. Please set build flag %s",
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"CTX_INCLUDE_AARCH32_REGS = 0\n");
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panic();
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}
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#endif
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/* Get the image descriptor. */
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desc = bl1_plat_get_image_desc(image_id);
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assert(desc != NULL);
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/* Get the entry point info. */
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next_bl_ep = &desc->ep_info;
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/* Get the image security state. */
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security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
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/* Setup the Secure/Non-Secure context if not done already. */
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if (cm_get_context(security_state) == NULL) {
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cm_set_context(&bl1_cpu_context[security_state], security_state);
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}
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/* Prepare the SPSR for the next BL image. */
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next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
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(uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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/* Allow platform to make change */
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bl1_plat_set_ep_info(image_id, next_bl_ep);
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/* Prepare context for the next EL */
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cm_prepare_el2_exit();
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/* Indicate that image is in execution state. */
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desc->state = IMAGE_STATE_EXECUTED;
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print_entry_point_info(next_bl_ep);
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}
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@ -43,14 +43,6 @@ func bl1_entrypoint
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*/
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bl bl1_setup
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#if ENABLE_PAUTH
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/* --------------------------------------------------------------------
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* Program APIAKey_EL1 and enable pointer authentication.
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* --------------------------------------------------------------------
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*/
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bl pauth_init_enable_el2
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#endif /* ENABLE_PAUTH */
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/* --------------------------------------------------------------------
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* Initialize platform and jump to our c-entry point
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* for this type of reset.
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@ -85,15 +77,6 @@ func bl1_run_next_image
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*/
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bl clear_all_mpu_regions
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Disable pointer authentication before jumping
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* to next boot image.
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* ---------------------------------------------
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*/
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bl pauth_disable_el2
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#endif /* ENABLE_PAUTH */
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/* --------------------------------------------------
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* Do the transition to next boot image.
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* --------------------------------------------------
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@ -25,6 +25,8 @@
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#include <platform_def.h>
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void cm_prepare_el2_exit(void);
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void bl1_run_next_image(const struct entry_point_info *bl_ep_info);
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/*******************************************************************************
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@ -39,13 +41,6 @@ void bl1_transfer_bl33(void)
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/* Get the image id of next image to load and run. */
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image_id = bl1_plat_get_next_image_id();
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#if ENABLE_PAUTH
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/*
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* Disable pointer authentication before running next boot image
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*/
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pauth_disable_el2();
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#endif /* ENABLE_PAUTH */
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Disable watchdog before leaving BL1 */
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plat_arm_secure_wdt_stop();
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@ -96,12 +91,6 @@ void bl1_load_bl33(void)
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NOTICE("BL1: Booting BL33\n");
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}
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static void bl1_load_bl2(void);
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#if ENABLE_PAUTH
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uint64_t bl1_apiakey[2];
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#endif
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/*******************************************************************************
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* Helper utility to calculate the BL2 memory layout taking into consideration
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* the BL1 RW data assuming that it is at the top of the memory layout.
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@ -123,6 +112,53 @@ void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
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flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
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}
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/*******************************************************************************
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* This function prepares for entry to BL33
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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unsigned int mode = MODE_EL1;
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image_desc_t *desc;
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entry_point_info_t *next_bl_ep;
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#if CTX_INCLUDE_AARCH32_REGS
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/*
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* Ensure that the build flag to save AArch32 system registers in CPU
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* context is not set for AArch64-only platforms.
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*/
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if (el_implemented(1) == EL_IMPL_A64ONLY) {
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ERROR("EL1 supports AArch64-only. Please set build flag %s",
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"CTX_INCLUDE_AARCH32_REGS = 0\n");
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panic();
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}
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#endif
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/* Get the image descriptor. */
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desc = bl1_plat_get_image_desc(image_id);
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assert(desc != NULL);
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/* Get the entry point info. */
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next_bl_ep = &desc->ep_info;
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/* FVP-R is only secure */
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assert(GET_SECURITY_STATE(next_bl_ep->h.attr) == SECURE);
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/* Prepare the SPSR for the next BL image. */
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next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
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(uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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/* Allow platform to make change */
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bl1_plat_set_ep_info(image_id, next_bl_ep);
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/* Prepare context for the next EL */
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cm_prepare_el2_exit();
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/* Indicate that image is in execution state. */
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desc->state = IMAGE_STATE_EXECUTED;
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print_entry_point_info(next_bl_ep);
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}
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|
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/*******************************************************************************
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* Setup function for BL1.
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******************************************************************************/
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@ -133,14 +169,6 @@ void bl1_setup(void)
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|
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/* Perform late platform-specific setup */
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bl1_plat_arch_setup();
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#if CTX_INCLUDE_PAUTH_REGS
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/*
|
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* Assert that the ARMv8.3-PAuth registers are present or an access
|
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* fault will be triggered when they are being saved or restored.
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*/
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assert(is_armv8_3_pauth_present());
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#endif /* CTX_INCLUDE_PAUTH_REGS */
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}
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/*******************************************************************************
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|
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@ -199,12 +227,6 @@ void bl1_main(void)
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/* Perform platform setup in BL1. */
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bl1_platform_setup();
|
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|
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#if ENABLE_PAUTH
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/* Store APIAKey_EL1 key */
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bl1_apiakey[0] = read_apiakeylo_el1();
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bl1_apiakey[1] = read_apiakeyhi_el1();
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#endif /* ENABLE_PAUTH */
|
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/* Get the image id of next image to load and run. */
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image_id = bl1_plat_get_next_image_id();
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|
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|
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@ -212,9 +234,7 @@ void bl1_main(void)
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* We currently interpret any image id other than
|
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* BL2_IMAGE_ID as the start of firmware update.
|
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*/
|
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if (image_id == BL2_IMAGE_ID) {
|
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bl1_load_bl2();
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} else if (image_id == BL33_IMAGE_ID) {
|
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if (image_id == BL33_IMAGE_ID) {
|
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bl1_load_bl33();
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} else {
|
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NOTICE("BL1-FWU: *******FWU Process Started*******\n");
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|
|
@ -227,48 +247,6 @@ void bl1_main(void)
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bl1_transfer_bl33();
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}
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/*******************************************************************************
|
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* This function locates and loads the BL2 raw binary image in the trusted SRAM.
|
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* Called by the primary cpu after a cold boot.
|
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* TODO: Add support for alternative image load mechanism e.g using virtio/elf
|
||||
* loader etc.
|
||||
******************************************************************************/
|
||||
static void bl1_load_bl2(void)
|
||||
{
|
||||
image_desc_t *desc;
|
||||
image_info_t *info;
|
||||
int err;
|
||||
|
||||
/* Get the image descriptor */
|
||||
desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
|
||||
assert(desc != NULL);
|
||||
|
||||
/* Get the image info */
|
||||
info = &desc->image_info;
|
||||
INFO("BL1: Loading BL2\n");
|
||||
|
||||
err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
|
||||
if (err != 0) {
|
||||
ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
|
||||
plat_error_handler(err);
|
||||
}
|
||||
|
||||
err = load_auth_image(BL2_IMAGE_ID, info);
|
||||
if (err != 0) {
|
||||
ERROR("Failed to load BL2 firmware.\n");
|
||||
plat_error_handler(err);
|
||||
}
|
||||
|
||||
/* Allow platform to handle image information. */
|
||||
err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
|
||||
if (err != 0) {
|
||||
ERROR("Failure in post image load handling of BL2 (%d)\n", err);
|
||||
plat_error_handler(err);
|
||||
}
|
||||
|
||||
NOTICE("BL1: Booting BL2\n");
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function called just before handing over to the next BL to inform the user
|
||||
* about the boot progress. In debug mode, also print details about the BL
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <common/debug.h>
|
||||
|
||||
#include <drivers/arm/cci.h>
|
||||
#include <drivers/arm/ccn.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/arm/sp804_delay_timer.h>
|
||||
#include <drivers/generic_delay_timer.h>
|
||||
|
|
@ -80,7 +79,6 @@ const mmap_region_t plat_arm_mmap[] = {
|
|||
|
||||
ARM_CASSERT_MMAP
|
||||
|
||||
#if FVP_R_INTERCONNECT_DRIVER != FVP_R_CCN
|
||||
static const int fvp_cci400_map[] = {
|
||||
PLAT_FVP_R_CCI400_CLUS0_SL_PORT,
|
||||
PLAT_FVP_R_CCI400_CLUS1_SL_PORT,
|
||||
|
|
@ -103,7 +101,6 @@ static unsigned int get_interconnect_master(void)
|
|||
assert(master < FVP_R_CLUSTER_COUNT);
|
||||
return master;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the platform config for future decision making
|
||||
|
|
@ -198,14 +195,6 @@ void __init fvp_config_setup(void)
|
|||
|
||||
void __init fvp_interconnect_init(void)
|
||||
{
|
||||
#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
|
||||
if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
|
||||
ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
|
||||
panic();
|
||||
}
|
||||
|
||||
plat_arm_interconnect_init();
|
||||
#else
|
||||
uintptr_t cci_base = 0U;
|
||||
const int *cci_map = NULL;
|
||||
unsigned int map_size = 0U;
|
||||
|
|
@ -226,14 +215,10 @@ void __init fvp_interconnect_init(void)
|
|||
assert(cci_base != 0U);
|
||||
assert(cci_map != NULL);
|
||||
cci_init(cci_base, cci_map, map_size);
|
||||
#endif
|
||||
}
|
||||
|
||||
void fvp_interconnect_enable(void)
|
||||
{
|
||||
#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
|
||||
plat_arm_interconnect_enter_coherency();
|
||||
#else
|
||||
unsigned int master;
|
||||
|
||||
if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
|
||||
|
|
@ -241,14 +226,10 @@ void fvp_interconnect_enable(void)
|
|||
master = get_interconnect_master();
|
||||
cci_enable_snoop_dvm_reqs(master);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void fvp_interconnect_disable(void)
|
||||
{
|
||||
#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
|
||||
plat_arm_interconnect_exit_coherency();
|
||||
#else
|
||||
unsigned int master;
|
||||
|
||||
if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
|
||||
|
|
@ -256,7 +237,6 @@ void fvp_interconnect_disable(void)
|
|||
master = get_interconnect_master();
|
||||
cci_disable_snoop_dvm_reqs(master);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <asm_macros.S>
|
||||
|
||||
.global el2_exit
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* The mechanism, from el3_exit, is not used in this v8-R64 implementation.
|
||||
* ------------------------------------------------------------------
|
||||
*/
|
||||
func el2_exit
|
||||
exception_return
|
||||
endfunc el2_exit
|
||||
|
|
@ -41,6 +41,7 @@ el2_panic:
|
|||
|
||||
_panic_handler:
|
||||
/* Pass to plat_panic_handler the address from where el2_panic was
|
||||
* called, not the address of the call from el2_panic. */
|
||||
* called, not the address of the call from el2_panic.
|
||||
*/
|
||||
mov x30, x6
|
||||
b plat_panic_handler
|
||||
|
|
|
|||
|
|
@ -9,28 +9,18 @@
|
|||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#ifndef FVP_R_CLUSTER_COUNT
|
||||
#error "FVP_R_CLUSTER_COUNT is not set in makefile"
|
||||
#endif
|
||||
|
||||
#ifndef FVP_R_MAX_CPUS_PER_CLUSTER
|
||||
#error "FVP_R_MAX_CPUS_PER_CLUSTER is not set in makefile"
|
||||
#endif
|
||||
|
||||
#ifndef FVP_R_MAX_PE_PER_CPU
|
||||
#error "FVP_R_MAX_PE_PER_CPU is not set in makefile"
|
||||
#endif
|
||||
|
||||
#define FVP_R_PRIMARY_CPU 0x0
|
||||
|
||||
/* Defines for the Interconnect build selection */
|
||||
#define FVP_R_CCI 1
|
||||
#define FVP_R_CCN 2
|
||||
/******************************************************************************
|
||||
* FVP-R topology constants
|
||||
*****************************************************************************/
|
||||
#define FVP_R_CLUSTER_COUNT 2
|
||||
#define FVP_R_MAX_CPUS_PER_CLUSTER 4
|
||||
#define FVP_R_MAX_PE_PER_CPU 1
|
||||
#define FVP_R_PRIMARY_CPU 0x0
|
||||
|
||||
/******************************************************************************
|
||||
* Definition of platform soc id
|
||||
*****************************************************************************/
|
||||
#define FVP_R_SOC_ID 0
|
||||
#define FVP_R_SOC_ID 0
|
||||
|
||||
/*******************************************************************************
|
||||
* FVP_R memory map related constants
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
.globl plat_secondary_cold_boot_setup
|
||||
.globl plat_get_my_entrypoint
|
||||
.globl plat_is_my_cpu_primary
|
||||
.globl plat_arm_calc_core_pos
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void plat_secondary_cold_boot_setup (void);
|
||||
|
|
@ -127,40 +126,3 @@ func plat_is_my_cpu_primary
|
|||
cset w0, eq
|
||||
ret
|
||||
endfunc plat_is_my_cpu_primary
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
|
||||
*
|
||||
* Function to calculate the core position on FVP_R.
|
||||
*
|
||||
* (ClusterId * FVP_R_MAX_CPUS_PER_CLUSTER * FVP_R_MAX_PE_PER_CPU) +
|
||||
* (CPUId * FVP_R_MAX_PE_PER_CPU) +
|
||||
* ThreadId
|
||||
*
|
||||
* which can be simplified as:
|
||||
*
|
||||
* ((ClusterId * FVP_R_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_R_MAX_PE_PER_CPU)
|
||||
* + ThreadId
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func plat_arm_calc_core_pos
|
||||
/*
|
||||
* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
|
||||
* look as if in a multi-threaded implementation.
|
||||
*/
|
||||
tst x0, #MPIDR_MT_MASK
|
||||
lsl x3, x0, #MPIDR_AFFINITY_BITS
|
||||
csel x3, x3, x0, eq
|
||||
|
||||
/* Extract individual affinity fields from MPIDR */
|
||||
ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
|
||||
/* Compute linear position */
|
||||
mov x4, #FVP_R_MAX_CPUS_PER_CLUSTER
|
||||
madd x1, x2, x4, x1
|
||||
mov x5, #FVP_R_MAX_PE_PER_CPU
|
||||
madd x0, x1, x5, x0
|
||||
ret
|
||||
endfunc plat_arm_calc_core_pos
|
||||
|
|
|
|||
|
|
@ -1,59 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <lib/el3_runtime/cpu_data.h>
|
||||
|
||||
.global pauth_init_enable_el2
|
||||
.global pauth_disable_el2
|
||||
|
||||
/* -------------------------------------------------------------
|
||||
* File contains EL2 versions of EL3 funcs in:
|
||||
* .../lib/extensions/pauth/pauth_helpers.S
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* -------------------------------------------------------------
|
||||
* Program APIAKey_EL1 and enable pointer authentication in EL2
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
func pauth_init_enable_el2
|
||||
stp x29, x30, [sp, #-16]!
|
||||
|
||||
/* Initialize platform key */
|
||||
bl plat_init_apkey
|
||||
|
||||
/* Program instruction key A used by the Trusted Firmware */
|
||||
msr APIAKeyLo_EL1, x0
|
||||
msr APIAKeyHi_EL1, x1
|
||||
|
||||
/* Enable pointer authentication */
|
||||
mrs x0, sctlr_el2
|
||||
orr x0, x0, #SCTLR_EnIA_BIT
|
||||
|
||||
#if ENABLE_BTI
|
||||
/* Enable PAC branch type compatibility */
|
||||
bic x0, x0, #SCTLR_BT_BIT
|
||||
#endif
|
||||
msr sctlr_el2, x0
|
||||
isb
|
||||
|
||||
ldp x29, x30, [sp], #16
|
||||
ret
|
||||
endfunc pauth_init_enable_el2
|
||||
|
||||
/* -------------------------------------------------------------
|
||||
* Disable pointer authentication in EL2
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
func pauth_disable_el2
|
||||
mrs x0, sctlr_el2
|
||||
bic x0, x0, #SCTLR_EnIA_BIT
|
||||
msr sctlr_el2, x0
|
||||
isb
|
||||
ret
|
||||
endfunc pauth_disable_el2
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef PLAT_LD_S
|
||||
#define PLAT_LD_S
|
||||
|
||||
#include <plat/arm/common/arm_tzc_dram.ld.S>
|
||||
|
||||
#endif /* PLAT_LD_S */
|
||||
|
|
@ -210,10 +210,6 @@
|
|||
#define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT 5
|
||||
#define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT 6
|
||||
|
||||
/* CCN related constants. Only CCN 502 is currently supported */
|
||||
#define PLAT_ARM_CCN_BASE UL(0xae000000)
|
||||
#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
|
||||
|
||||
/* System timer related constants */
|
||||
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
|
||||
|
||||
|
|
|
|||
|
|
@ -15,47 +15,12 @@ NEED_BL32 := no
|
|||
|
||||
override CTX_INCLUDE_AARCH32_REGS := 0
|
||||
|
||||
# Default cluster count for FVP_R
|
||||
FVP_R_CLUSTER_COUNT := 2
|
||||
|
||||
# Default number of CPUs per cluster on FVP_R
|
||||
FVP_R_MAX_CPUS_PER_CLUSTER := 4
|
||||
|
||||
# Default number of threads per CPU on FVP_R
|
||||
FVP_R_MAX_PE_PER_CPU := 1
|
||||
|
||||
# Use MPU-based memory management:
|
||||
XLAT_MPU_LIB_V1 := 1
|
||||
|
||||
# Pass FVP_R_CLUSTER_COUNT to the build system.
|
||||
$(eval $(call add_define,FVP_R_CLUSTER_COUNT))
|
||||
|
||||
# Pass FVP_R_MAX_CPUS_PER_CLUSTER to the build system.
|
||||
$(eval $(call add_define,FVP_R_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
# Pass FVP_R_MAX_PE_PER_CPU to the build system.
|
||||
$(eval $(call add_define,FVP_R_MAX_PE_PER_CPU))
|
||||
|
||||
# Sanity check the cluster count and if FVP_R_CLUSTER_COUNT <= 2,
|
||||
# choose the CCI driver , else the CCN driver
|
||||
ifeq ($(FVP_R_CLUSTER_COUNT), 0)
|
||||
$(error "Incorrect cluster count specified for FVP_R port")
|
||||
else ifeq ($(FVP_R_CLUSTER_COUNT),$(filter $(FVP_R_CLUSTER_COUNT),1 2))
|
||||
FVP_R_INTERCONNECT_DRIVER := FVP_R_CCI
|
||||
else
|
||||
FVP_R_INTERCONNECT_DRIVER := FVP_R_CCN
|
||||
endif
|
||||
|
||||
$(eval $(call add_define,FVP_R_INTERCONNECT_DRIVER))
|
||||
|
||||
ifeq (${FVP_R_INTERCONNECT_DRIVER}, FVP_R_CCI)
|
||||
# FVP R will not have more than 2 clusters so just use CCI interconnect
|
||||
FVP_R_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
|
||||
else ifeq (${FVP_R_INTERCONNECT_DRIVER}, FVP_R_CCN)
|
||||
FVP_R_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
|
||||
plat/arm/common/arm_ccn.c
|
||||
else
|
||||
$(error "Incorrect CCN driver chosen on FVP_R port")
|
||||
endif
|
||||
|
||||
|
||||
include plat/arm/board/common/board_common.mk
|
||||
include plat/arm/common/arm_common.mk
|
||||
|
|
@ -64,17 +29,14 @@ PLAT_INCLUDES := -Iplat/arm/board/fvp_r/include
|
|||
|
||||
FVP_R_BL_COMMON_SOURCES := plat/arm/board/fvp_r/fvp_r_common.c \
|
||||
plat/arm/board/fvp_r/fvp_r_context_mgmt.c \
|
||||
plat/arm/board/fvp_r/fvp_r_context.S \
|
||||
plat/arm/board/fvp_r/fvp_r_debug.S \
|
||||
plat/arm/board/fvp_r/fvp_r_err.c \
|
||||
plat/arm/board/fvp_r/fvp_r_helpers.S \
|
||||
plat/arm/board/fvp_r/fvp_r_misc_helpers.S \
|
||||
plat/arm/board/fvp_r/fvp_r_pauth_helpers.S
|
||||
plat/arm/board/fvp_r/fvp_r_misc_helpers.S
|
||||
|
||||
FVP_R_BL1_SOURCES := plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c \
|
||||
plat/arm/board/fvp_r/fvp_r_bl1_setup.c \
|
||||
plat/arm/board/fvp_r/fvp_r_io_storage.c \
|
||||
plat/arm/board/fvp_r/fvp_r_bl1_context_mgmt.c \
|
||||
plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S \
|
||||
plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S \
|
||||
plat/arm/board/fvp_r/fvp_r_bl1_main.c
|
||||
|
|
@ -82,17 +44,13 @@ FVP_R_BL1_SOURCES := plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c \
|
|||
FVP_R_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
|
||||
|
||||
FVP_R_DYNC_CFG_SOURCES := common/fdt_wrappers.c \
|
||||
common/uuid.c \
|
||||
plat/arm/common/arm_dyn_cfg.c \
|
||||
plat/arm/common/arm_dyn_cfg_helpers.c
|
||||
plat/arm/common/arm_dyn_cfg.c
|
||||
|
||||
ifeq (${TRUSTED_BOARD_BOOT},1)
|
||||
FVP_R_AUTH_SOURCES := drivers/auth/auth_mod.c \
|
||||
drivers/auth/crypto_mod.c \
|
||||
drivers/auth/img_parser_mod.c \
|
||||
lib/fconf/fconf_tbbr_getter.c \
|
||||
bl1/tbbr/tbbr_img_desc.c \
|
||||
plat/arm/common/arm_bl1_fwu.c \
|
||||
plat/common/tbbr/plat_tbbr.c \
|
||||
drivers/auth/tbbr/tbbr_cot_bl1_r64.c \
|
||||
drivers/auth/tbbr/tbbr_cot_common.c \
|
||||
|
|
@ -125,11 +83,6 @@ override BL1_SOURCES := drivers/arm/sp805/sp805.c \
|
|||
drivers/io/io_storage.c \
|
||||
drivers/io/io_semihosting.c \
|
||||
lib/cpus/aarch64/cpu_helpers.S \
|
||||
lib/cpus/errata_report.c \
|
||||
lib/cpus/aarch64/dsu_helpers.S \
|
||||
lib/el3_runtime/aarch64/context.S \
|
||||
lib/el3_runtime/aarch64/context_mgmt.c \
|
||||
lib/fconf/fconf.c \
|
||||
lib/fconf/fconf_dyn_cfg_getter.c \
|
||||
lib/semihosting/semihosting.c \
|
||||
lib/semihosting/${ARCH}/semihosting_call.S \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue