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feat(spmd): initialize SCR_EL3.EEL2 bit at RESET

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SCR_EL3.EEL2 bit enabled denotes that the system has S-EL2 present and
enabled, Ideally this bit is constant throughout the lifetime and
should not be modified. Currently this bit is initialized in the context
mgmt code where each world copy of the SCR_EL3 register has this bit set
to 1, but for the time duration between the RESET and the first exit to
a lower EL this bit is zero.

Modifying SCR_EL3.EEL2 along with EA bit at RESET does also helps in
mitigating against ERRATA_V2_3099206.

For details on Neoverse V2 errata 3099206, refer the SDEN document
given below.
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If8b2bdbb19bc65391a33dd34cc9824a0203ae4b1
This commit is contained in:
Manish Pandey 2024-01-29 21:17:33 +00:00
parent 89b9d96573
commit 8815cdaf57
1 changed files with 12 additions and 0 deletions

12
include/arch/aarch64/el3_common_macros.S
View file

@ -64,9 +64,21 @@
*
* SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
* to EL3 when executing at any EL.
*
* SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled.
*
* NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate
* against ERRATA_V2_3099206.
* ---------------------------------------------------------------------
*/
mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT)
#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
mrs x1, id_aa64pfr0_el1
and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
cbz x1, 1f
orr x0, x0, #SCR_EEL2_BIT
#endif
1:
msr scr_el3, x0
/* ---------------------------------------------------------------------