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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge changes from topic "sm_bk/errata_refactor" into integration
* changes: refactor(cpus): convert the Cortex-A78AE to use cpu helpers refactor(cpus): convert the Denver cpu to use the errata framework refactor(cpus): convert the Cortex-A78AE to use the errata framework refactor(cpus): convert the Cortex-A5 to use the errata framework refactor(cpus): convert the Cortex-A77 to use the bit set helpers refactor(cpus): convert the Cortex-A77 to use the errata framework refactor(cpus): reorder Cortex-A77 errata by ascending order
This commit is contained in:
Bipin Ravi
TrustedFirmware Code Review
commit
87e3d4f1ac
4 changed files with 101 additions and 537 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -69,14 +69,7 @@ func cortex_a5_cluster_pwr_dwn
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b cortex_a5_disable_smp
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endfunc cortex_a5_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A5. Must follow AAPCS.
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*/
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func cortex_a5_errata_report
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bx lr
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endfunc cortex_a5_errata_report
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#endif
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errata_report_shim cortex_a5
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declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \
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cortex_a5_reset_func, \
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -26,26 +26,13 @@
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wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1508412.
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* This applies only to revision <= r1p0 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1508412_wa
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/*
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* Compare x0 against revision r1p0
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*/
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mov x17, x30
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bl check_errata_1508412
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cbz x0, 3f
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/*
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* Compare x0 against revision r0p0
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*/
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bl check_errata_1508412_0
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workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
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/* move cpu revision in again and compare against r0p0 */
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mov x0, x7
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mov x1, #CPU_REV(0, 0)
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bl cpu_rev_var_ls
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cbz x0, 1f
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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@ -75,64 +62,30 @@ func errata_a77_1508412_wa
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2:
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ldr x0, =0x04004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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isb
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3:
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ret x17
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endfunc errata_a77_1508412_wa
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workaround_reset_end cortex_a77, ERRATUM(1508412)
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func check_errata_1508412
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1508412
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check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0)
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func check_errata_1508412_0
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mov x1, #0x0
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b cpu_rev_var_ls
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endfunc check_errata_1508412_0
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workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578
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sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2
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workaround_reset_end cortex_a77, ERRATUM(1791578)
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1925769.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1925769_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1925769
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1)
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/* Set bit 8 in ECTLR_EL1 */
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mrs x1, CORTEX_A77_CPUECTLR_EL1
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orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
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msr CORTEX_A77_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1925769_wa
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workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714
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/* Disable allocation of splintered pages in the L2 TLB */
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sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53
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workaround_reset_end cortex_a77, ERRATUM(1800714)
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func check_errata_1925769
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1925769
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check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1)
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1946167.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1946167_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1946167
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cbz x0, 1f
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workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
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sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
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workaround_reset_end cortex_a77, ERRATUM(1925769)
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check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167
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ldr x0,=0x4
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3900002
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@ -159,188 +112,42 @@ func errata_a77_1946167_wa
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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workaround_reset_end cortex_a77, ERRATUM(1946167)
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isb
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1:
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ret x17
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endfunc errata_a77_1946167_wa
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check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1)
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func check_errata_1946167
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1946167
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workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587
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sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0
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workaround_reset_end cortex_a77, ERRATUM(2356587)
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1791578.
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1791578_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1791578
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cbz x0, 1f
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, CORTEX_A77_ACTLR2_EL1
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orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
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msr CORTEX_A77_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1791578_wa
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func check_errata_1791578
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1791578
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #2356587.
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_2356587_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2356587
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cbz x0, 1f
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/* Set bit 0 in ACTLR2_EL1 */
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mrs x1, CORTEX_A77_ACTLR2_EL1
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orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0
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msr CORTEX_A77_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_2356587_wa
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func check_errata_2356587
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_2356587
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/* -----------------------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #2743100
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* -----------------------------------------------------------------
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*/
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func errata_a77_2743100_wa
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mov x17, x30
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bl check_errata_2743100
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1)
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workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
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/* dsb before isb of power down sequence */
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dsb sy
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1:
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ret x17
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endfunc errata_a77_2743100_wa
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workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB
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func check_errata_2743100
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_2743100
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check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1)
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1800714.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1800714_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1800714
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cbz x0, 1f
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/* Disable allocation of splintered pages in the L2 TLB */
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mrs x1, CORTEX_A77_CPUECTLR_EL1
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orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
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msr CORTEX_A77_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1800714_wa
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func check_errata_1800714
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1800714
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a77_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A77_1508412
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mov x0, x18
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bl errata_a77_1508412_wa
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#endif
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#if ERRATA_A77_1925769
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mov x0, x18
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bl errata_a77_1925769_wa
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#endif
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#if ERRATA_A77_1946167
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mov x0, x18
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bl errata_a77_1946167_wa
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#endif
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#if ERRATA_A77_1791578
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mov x0, x18
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bl errata_a77_1791578_wa
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#endif
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#if ERRATA_A77_2356587
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mov x0, x18
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bl errata_a77_2356587_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A77 generic vectors are overridden to apply errata
|
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* mitigation on exception entry from lower ELs.
|
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*/
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adr x0, wa_cve_vbar_cortex_a77
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a77, CVE(2022, 23960)
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#if ERRATA_A77_1800714
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mov x0, x18
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bl errata_a77_1800714_wa
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#endif
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check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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|
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isb
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ret x19
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endfunc cortex_a77_reset_func
|
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/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
|
||||
* -------------------------------------------------
|
||||
*/
|
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cpu_reset_func_start cortex_a77
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cpu_reset_func_end cortex_a77
|
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|
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/* ---------------------------------------------
|
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* HW will do the cache maintenance while powering down
|
||||
|
|
@ -351,48 +158,16 @@ func cortex_a77_core_pwr_dwn
|
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* Enable CPU power down bit in power control register
|
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* ---------------------------------------------
|
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*/
|
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mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A77_CPUPWRCTLR_EL1, x0
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#if ERRATA_A77_2743100
|
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mov x15, x30
|
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bl cpu_get_rev_var
|
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bl errata_a77_2743100_wa
|
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mov x30, x15
|
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#endif /* ERRATA_A77_2743100 */
|
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sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
|
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CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
|
||||
|
||||
apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
|
||||
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_a77_core_pwr_dwn
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Errata printing function for Cortex-A77. Must follow AAPCS.
|
||||
*/
|
||||
func cortex_a77_errata_report
|
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stp x8, x30, [sp, #-16]!
|
||||
|
||||
bl cpu_get_rev_var
|
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mov x8, x0
|
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|
||||
/*
|
||||
* Report all errata. The revision-variant information is passed to
|
||||
* checking functions of each errata.
|
||||
*/
|
||||
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
|
||||
report_errata ERRATA_A77_1791578, cortex_a77, 1791578
|
||||
report_errata ERRATA_A77_1800714, cortex_a77, 1800714
|
||||
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
|
||||
report_errata ERRATA_A77_1946167, cortex_a77, 1946167
|
||||
report_errata ERRATA_A77_2356587, cortex_a77, 2356587
|
||||
report_errata ERRATA_A77_2743100, cortex_a77, 2743100
|
||||
report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
endfunc cortex_a77_errata_report
|
||||
#endif
|
||||
|
||||
|
||||
errata_report_shim cortex_a77
|
||||
/* ---------------------------------------------
|
||||
* This function provides Cortex-A77 specific
|
||||
* register information for crash reporting.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -22,50 +22,13 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for A78 AE Erratum 1941500.
|
||||
* This applies to revisions r0p0 and r0p1 of A78 AE.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_a78_ae_1941500_wa
|
||||
/* Compare x0 against revisions r0p0 - r0p1 */
|
||||
mov x17, x30
|
||||
bl check_errata_1941500
|
||||
cbz x0, 1f
|
||||
workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
|
||||
sysreg_bit_clear CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
|
||||
workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
|
||||
|
||||
/* Set bit 8 in ECTLR_EL1 */
|
||||
mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
|
||||
bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
|
||||
msr CORTEX_A78_AE_CPUECTLR_EL1, x0
|
||||
isb
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a78_ae_1941500_wa
|
||||
|
||||
func check_errata_1941500
|
||||
/* Applies to revisions r0p0 and r0p1. */
|
||||
mov x1, #CPU_REV(0, 0)
|
||||
mov x2, #CPU_REV(0, 1)
|
||||
b cpu_rev_var_range
|
||||
endfunc check_errata_1941500
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for A78 AE Erratum 1951502.
|
||||
* This applies to revisions r0p0 and r0p1 of A78 AE.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_a78_ae_1951502_wa
|
||||
/* Compare x0 against revisions r0p0 - r0p1 */
|
||||
mov x17, x30
|
||||
bl check_errata_1951502
|
||||
cbz x0, 1f
|
||||
check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1)
|
||||
|
||||
workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
|
||||
msr S3_6_c15_c8_0, xzr
|
||||
ldr x0, =0x10E3900002
|
||||
msr S3_6_c15_c8_2, x0
|
||||
|
|
@ -91,33 +54,11 @@ func errata_a78_ae_1951502_wa
|
|||
msr S3_6_c15_c8_3, x0
|
||||
ldr x0, =0x2001003FF
|
||||
msr S3_6_c15_c8_1, x0
|
||||
workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
|
||||
|
||||
isb
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a78_ae_1951502_wa
|
||||
|
||||
func check_errata_1951502
|
||||
/* Applies to revisions r0p0 and r0p1. */
|
||||
mov x1, #CPU_REV(0, 0)
|
||||
mov x2, #CPU_REV(0, 1)
|
||||
b cpu_rev_var_range
|
||||
endfunc check_errata_1951502
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for A78 AE Erratum 2376748.
|
||||
* This applies to revisions r0p0 and r0p1 of A78 AE.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_a78_ae_2376748_wa
|
||||
/* Compare x0 against revisions r0p0 - r0p1 */
|
||||
mov x17, x30
|
||||
bl check_errata_2376748
|
||||
cbz x0, 1f
|
||||
check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1)
|
||||
|
||||
workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
|
||||
/* -------------------------------------------------------
|
||||
* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
|
||||
* behave like PLD/PRFM LD and not cause invalidations to
|
||||
|
|
@ -126,104 +67,42 @@ func errata_a78_ae_2376748_wa
|
|||
* that share data.
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
mrs x0, CORTEX_A78_AE_ACTLR2_EL1
|
||||
orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
|
||||
msr CORTEX_A78_AE_ACTLR2_EL1, x0
|
||||
isb
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a78_ae_2376748_wa
|
||||
sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0
|
||||
workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
|
||||
|
||||
func check_errata_2376748
|
||||
/* Applies to revisions r0p0 and r0p1. */
|
||||
mov x1, #CPU_REV(0, 0)
|
||||
mov x2, #CPU_REV(0, 1)
|
||||
b cpu_rev_var_range
|
||||
endfunc check_errata_2376748
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for A78 AE Erratum 2395408.
|
||||
* This applies to revisions r0p0 and r0p1 of A78 AE.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_a78_ae_2395408_wa
|
||||
/* Compare x0 against revisions r0p0 - r0p1 */
|
||||
mov x17, x30
|
||||
bl check_errata_2395408
|
||||
cbz x0, 1f
|
||||
check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 1)
|
||||
|
||||
workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
|
||||
/* --------------------------------------------------------
|
||||
* Disable folding of demand requests into older prefetches
|
||||
* with L2 miss requests outstanding by setting the
|
||||
* CPUACTLR2_EL1[40] to 1.
|
||||
* --------------------------------------------------------
|
||||
*/
|
||||
mrs x0, CORTEX_A78_AE_ACTLR2_EL1
|
||||
orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
|
||||
msr CORTEX_A78_AE_ACTLR2_EL1, x0
|
||||
isb
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a78_ae_2395408_wa
|
||||
sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40
|
||||
workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
|
||||
|
||||
func check_errata_2395408
|
||||
/* Applies to revisions r0p0 and r0p1. */
|
||||
mov x1, #CPU_REV(0, 0)
|
||||
mov x2, #CPU_REV(0, 1)
|
||||
b cpu_rev_var_range
|
||||
endfunc check_errata_2395408
|
||||
check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1)
|
||||
|
||||
func check_errata_cve_2022_23960
|
||||
#if WORKAROUND_CVE_2022_23960
|
||||
mov x0, #ERRATA_APPLIES
|
||||
#else
|
||||
mov x0, #ERRATA_MISSING
|
||||
#endif
|
||||
ret
|
||||
endfunc check_errata_cve_2022_23960
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A78-AE
|
||||
* -------------------------------------------------
|
||||
workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
#if IMAGE_BL31
|
||||
/*
|
||||
* The Cortex-A78AE generic vectors are overridden to apply errata
|
||||
* mitigation on exception entry from lower ELs.
|
||||
*/
|
||||
func cortex_a78_ae_reset_func
|
||||
mov x19, x30
|
||||
bl cpu_get_rev_var
|
||||
mov x18, x0
|
||||
override_vector_table wa_cve_vbar_cortex_a78_ae
|
||||
#endif /* IMAGE_BL31 */
|
||||
workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
|
||||
|
||||
#if ERRATA_A78_AE_1941500
|
||||
mov x0, x18
|
||||
bl errata_a78_ae_1941500_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A78_AE_1951502
|
||||
mov x0, x18
|
||||
bl errata_a78_ae_1951502_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A78_AE_2376748
|
||||
mov x0, x18
|
||||
bl errata_a78_ae_2376748_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A78_AE_2395408
|
||||
mov x0, x18
|
||||
bl errata_a78_ae_2395408_wa
|
||||
#endif
|
||||
check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
cpu_reset_func_start cortex_a78_ae
|
||||
#if ENABLE_FEAT_AMU
|
||||
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
|
||||
mrs x0, actlr_el3
|
||||
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
|
||||
msr actlr_el3, x0
|
||||
sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
|
||||
|
||||
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
|
||||
mrs x0, actlr_el2
|
||||
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
|
||||
msr actlr_el2, x0
|
||||
sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
|
||||
|
||||
/* Enable group0 counters */
|
||||
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
|
||||
|
|
@ -233,19 +112,7 @@ func cortex_a78_ae_reset_func
|
|||
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
|
||||
msr CPUAMCNTENSET1_EL0, x0
|
||||
#endif
|
||||
|
||||
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
|
||||
/*
|
||||
* The Cortex-A78AE generic vectors are overridden to apply errata
|
||||
* mitigation on exception entry from lower ELs.
|
||||
*/
|
||||
adr x0, wa_cve_vbar_cortex_a78_ae
|
||||
msr vbar_el3, x0
|
||||
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
isb
|
||||
ret x19
|
||||
endfunc cortex_a78_ae_reset_func
|
||||
cpu_reset_func_end cortex_a78_ae
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
|
|
@ -256,37 +123,12 @@ func cortex_a78_ae_core_pwr_dwn
|
|||
* Enable CPU power down bit in power control register
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
|
||||
orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
|
||||
msr CORTEX_A78_CPUPWRCTLR_EL1, x0
|
||||
sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_a78_ae_core_pwr_dwn
|
||||
|
||||
/*
|
||||
* Errata printing function for cortex_a78_ae. Must follow AAPCS.
|
||||
*/
|
||||
#if REPORT_ERRATA
|
||||
func cortex_a78_ae_errata_report
|
||||
stp x8, x30, [sp, #-16]!
|
||||
|
||||
bl cpu_get_rev_var
|
||||
mov x8, x0
|
||||
|
||||
/*
|
||||
* Report all errata. The revision-variant information is passed to
|
||||
* checking functions of each errata.
|
||||
*/
|
||||
report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
|
||||
report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
|
||||
report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
|
||||
report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408
|
||||
report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
endfunc cortex_a78_ae_errata_report
|
||||
#endif
|
||||
errata_report_shim cortex_a78_ae
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* This function provides cortex_a78_ae specific
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -207,7 +207,14 @@ func denver_disable_dco
|
|||
2: ret
|
||||
endfunc denver_disable_dco
|
||||
|
||||
func check_errata_cve_2017_5715
|
||||
workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
|
||||
#if IMAGE_BL31
|
||||
adr x1, workaround_bpflush_runtime_exceptions
|
||||
msr vbar_el3, x1
|
||||
#endif
|
||||
workaround_reset_end denver, CVE(2017, 5715)
|
||||
|
||||
check_erratum_custom_start denver, CVE(2017, 5715)
|
||||
mov x0, #ERRATA_MISSING
|
||||
#if WORKAROUND_CVE_2017_5715
|
||||
/*
|
||||
|
|
@ -224,43 +231,9 @@ func check_errata_cve_2017_5715
|
|||
1:
|
||||
#endif
|
||||
ret
|
||||
endfunc check_errata_cve_2017_5715
|
||||
check_erratum_custom_end denver, CVE(2017, 5715)
|
||||
|
||||
func check_errata_cve_2018_3639
|
||||
#if WORKAROUND_CVE_2018_3639
|
||||
mov x0, #ERRATA_APPLIES
|
||||
#else
|
||||
mov x0, #ERRATA_MISSING
|
||||
#endif
|
||||
ret
|
||||
endfunc check_errata_cve_2018_3639
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Denver.
|
||||
* -------------------------------------------------
|
||||
*/
|
||||
func denver_reset_func
|
||||
|
||||
mov x19, x30
|
||||
|
||||
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
|
||||
/*
|
||||
* Check if the CPU supports the special instruction
|
||||
* required to flush the indirect branch predictor and
|
||||
* RSB. Support for this operation can be determined by
|
||||
* comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
|
||||
*/
|
||||
mrs x0, id_afr0_el1
|
||||
mov x1, #0x10000
|
||||
and x0, x0, x1
|
||||
cmp x0, #0
|
||||
adr x1, workaround_bpflush_runtime_exceptions
|
||||
mrs x2, vbar_el3
|
||||
csel x0, x1, x2, ne
|
||||
msr vbar_el3, x0
|
||||
#endif
|
||||
|
||||
#if WORKAROUND_CVE_2018_3639
|
||||
workaround_reset_start denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
|
||||
/*
|
||||
* Denver CPUs with DENVER_MIDR_PN3 or earlier, use different
|
||||
* bits in the ACTLR_EL3 register to disable speculative
|
||||
|
|
@ -277,8 +250,11 @@ func denver_reset_func
|
|||
msr actlr_el3, x0
|
||||
isb
|
||||
dsb sy
|
||||
#endif
|
||||
workaround_reset_end denver, CVE(2018, 3639)
|
||||
|
||||
check_erratum_chosen denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
|
||||
|
||||
cpu_reset_func_start denver
|
||||
/* ----------------------------------------------------
|
||||
* Reset ACTLR.PMSTATE to C1 state
|
||||
* ----------------------------------------------------
|
||||
|
|
@ -293,9 +269,7 @@ func denver_reset_func
|
|||
* ----------------------------------------------------
|
||||
*/
|
||||
bl denver_enable_dco
|
||||
|
||||
ret x19
|
||||
endfunc denver_reset_func
|
||||
cpu_reset_func_end denver
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* The CPU Ops core power down function for Denver.
|
||||
|
|
@ -322,27 +296,7 @@ func denver_cluster_pwr_dwn
|
|||
ret
|
||||
endfunc denver_cluster_pwr_dwn
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Errata printing function for Denver. Must follow AAPCS.
|
||||
*/
|
||||
func denver_errata_report
|
||||
stp x8, x30, [sp, #-16]!
|
||||
|
||||
bl cpu_get_rev_var
|
||||
mov x8, x0
|
||||
|
||||
/*
|
||||
* Report all errata. The revision-variant information is passed to
|
||||
* checking functions of each errata.
|
||||
*/
|
||||
report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
|
||||
report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
endfunc denver_errata_report
|
||||
#endif
|
||||
errata_report_shim denver
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function provides Denver specific
|
||||
|
|
@ -367,7 +321,7 @@ endfunc denver_cpu_reg_dump
|
|||
.macro denver_cpu_ops_wa midr
|
||||
declare_cpu_ops_wa denver, \midr, \
|
||||
denver_reset_func, \
|
||||
check_errata_cve_2017_5715, \
|
||||
check_erratum_denver_5715, \
|
||||
CPU_NO_EXTRA2_FUNC, \
|
||||
CPU_NO_EXTRA3_FUNC, \
|
||||
denver_core_pwr_dwn, \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue