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Merge changes from topic "sm_bk/errata_refactor" into integration

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* changes:
  refactor(cpus): convert the Cortex-A78AE to use cpu helpers
  refactor(cpus): convert the Denver cpu to use the errata framework
  refactor(cpus): convert the Cortex-A78AE to use the errata framework
  refactor(cpus): convert the Cortex-A5 to use the errata framework
  refactor(cpus): convert the Cortex-A77 to use the bit set helpers
  refactor(cpus): convert the Cortex-A77 to use the errata framework
  refactor(cpus): reorder Cortex-A77 errata by ascending order
This commit is contained in:
Bipin Ravi 2023-08-04 19:25:09 +02:00 • committed by TrustedFirmware Code Review
commit 87e3d4f1ac
4 changed files with 101 additions and 537 deletions
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11
lib/cpus/aarch32/cortex_a5.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -69,14 +69,7 @@ func cortex_a5_cluster_pwr_dwn
b cortex_a5_disable_smp b cortex_a5_disable_smp
endfunc cortex_a5_cluster_pwr_dwn endfunc cortex_a5_cluster_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_a5
/*
* Errata printing function for Cortex-A5. Must follow AAPCS.
*/
func cortex_a5_errata_report
bx lr
endfunc cortex_a5_errata_report
#endif
declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \ declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \
cortex_a5_reset_func, \ cortex_a5_reset_func, \

325
lib/cpus/aarch64/cortex_a77.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -26,26 +26,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
/* -------------------------------------------------- workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
* Errata Workaround for Cortex A77 Errata #1508412. /* move cpu revision in again and compare against r0p0 */
* This applies only to revision <= r1p0 of Cortex A77. mov x0, x7
* Inputs: mov x1, #CPU_REV(0, 0)
* x0: variant[4:7] and revision[0:3] of current cpu. bl cpu_rev_var_ls
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a77_1508412_wa
/*
* Compare x0 against revision r1p0
*/
mov x17, x30
bl check_errata_1508412
cbz x0, 3f
/*
* Compare x0 against revision r0p0
*/
bl check_errata_1508412_0
cbz x0, 1f cbz x0, 1f
ldr x0, =0x0 ldr x0, =0x0
msr CORTEX_A77_CPUPSELR_EL3, x0 msr CORTEX_A77_CPUPSELR_EL3, x0
ldr x0, =0x00E8400000 ldr x0, =0x00E8400000
@ -75,64 +62,30 @@ func errata_a77_1508412_wa
2: 2:
ldr x0, =0x04004003FF ldr x0, =0x04004003FF
msr CORTEX_A77_CPUPCR_EL3, x0 msr CORTEX_A77_CPUPCR_EL3, x0
isb workaround_reset_end cortex_a77, ERRATUM(1508412)
3:
ret x17
endfunc errata_a77_1508412_wa
func check_errata_1508412 check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0)
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1508412
func check_errata_1508412_0 workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578
mov x1, #0x0 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2
b cpu_rev_var_ls workaround_reset_end cortex_a77, ERRATUM(1791578)
endfunc check_errata_1508412_0
/* -------------------------------------------------- check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1)
* Errata Workaround for Cortex A77 Errata #1925769.
* This applies to revision <= r1p1 of Cortex A77.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a77_1925769_wa
/* Compare x0 against revision <= r1p1 */
mov x17, x30
bl check_errata_1925769
cbz x0, 1f
/* Set bit 8 in ECTLR_EL1 */ workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714
mrs x1, CORTEX_A77_CPUECTLR_EL1 /* Disable allocation of splintered pages in the L2 TLB */
orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53
msr CORTEX_A77_CPUECTLR_EL1, x1 workaround_reset_end cortex_a77, ERRATUM(1800714)
isb
1:
ret x17
endfunc errata_a77_1925769_wa
func check_errata_1925769 check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1)
/* Applies to everything <= r1p1 */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_1925769
/* -------------------------------------------------- workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
* Errata Workaround for Cortex A77 Errata #1946167. sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
* This applies to revision <= r1p1 of Cortex A77. workaround_reset_end cortex_a77, ERRATUM(1925769)
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a77_1946167_wa
/* Compare x0 against revision <= r1p1 */
mov x17, x30
bl check_errata_1946167
cbz x0, 1f
check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167
ldr x0,=0x4 ldr x0,=0x4
msr CORTEX_A77_CPUPSELR_EL3,x0 msr CORTEX_A77_CPUPSELR_EL3,x0
ldr x0,=0x10E3900002 ldr x0,=0x10E3900002
@ -159,188 +112,42 @@ func errata_a77_1946167_wa
msr CORTEX_A77_CPUPMR_EL3,x0 msr CORTEX_A77_CPUPMR_EL3,x0
ldr x0,=0x2001003FF ldr x0,=0x2001003FF
msr CORTEX_A77_CPUPCR_EL3,x0 msr CORTEX_A77_CPUPCR_EL3,x0
workaround_reset_end cortex_a77, ERRATUM(1946167)
isb check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1)
1:
ret x17
endfunc errata_a77_1946167_wa
func check_errata_1946167 workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587
/* Applies to everything <= r1p1 */ sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0
mov x1, #0x11 workaround_reset_end cortex_a77, ERRATUM(2356587)
b cpu_rev_var_ls
endfunc check_errata_1946167
/* -------------------------------------------------- check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1)
* Errata Workaround for Cortex A77 Errata #1791578.
* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a77_1791578_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_1791578
cbz x0, 1f
/* Set bit 2 in ACTLR2_EL1 */
mrs x1, CORTEX_A77_ACTLR2_EL1
orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
msr CORTEX_A77_ACTLR2_EL1, x1
isb
1:
ret x17
endfunc errata_a77_1791578_wa
func check_errata_1791578
/* Applies to r0p0, r1p0, and r1p1 right now */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_1791578
/* --------------------------------------------------
* Errata Workaround for Cortex A77 Errata #2356587.
* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a77_2356587_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2356587
cbz x0, 1f
/* Set bit 0 in ACTLR2_EL1 */
mrs x1, CORTEX_A77_ACTLR2_EL1
orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0
msr CORTEX_A77_ACTLR2_EL1, x1
isb
1:
ret x17
endfunc errata_a77_2356587_wa
func check_errata_2356587
/* Applies to r0p0, r1p0, and r1p1 right now */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_2356587
/* -----------------------------------------------------------------
* Errata Workaround for Cortex A77 Errata #2743100
* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* -----------------------------------------------------------------
*/
func errata_a77_2743100_wa
mov x17, x30
bl check_errata_2743100
cbz x0, 1f
workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
/* dsb before isb of power down sequence */ /* dsb before isb of power down sequence */
dsb sy dsb sy
1: workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB
ret x17
endfunc errata_a77_2743100_wa
func check_errata_2743100 check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1)
/* Applies to r0p0, r1p0, and r1p1 right now */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_2743100
func check_errata_cve_2022_23960 workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if WORKAROUND_CVE_2022_23960 #if IMAGE_BL31
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
/* --------------------------------------------------
* Errata Workaround for Cortex A77 Errata #1800714.
* This applies to revision <= r1p1 of Cortex A77.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a77_1800714_wa
/* Compare x0 against revision <= r1p1 */
mov x17, x30
bl check_errata_1800714
cbz x0, 1f
/* Disable allocation of splintered pages in the L2 TLB */
mrs x1, CORTEX_A77_CPUECTLR_EL1
orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
msr CORTEX_A77_CPUECTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a77_1800714_wa
func check_errata_1800714
/* Applies to everything <= r1p1 */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_1800714
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A77.
* Shall clobber: x0-x19
* -------------------------------------------------
*/
func cortex_a77_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A77_1508412
mov x0, x18
bl errata_a77_1508412_wa
#endif
#if ERRATA_A77_1925769
mov x0, x18
bl errata_a77_1925769_wa
#endif
#if ERRATA_A77_1946167
mov x0, x18
bl errata_a77_1946167_wa
#endif
#if ERRATA_A77_1791578
mov x0, x18
bl errata_a77_1791578_wa
#endif
#if ERRATA_A77_2356587
mov x0, x18
bl errata_a77_2356587_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/* /*
* The Cortex-A77 generic vectors are overridden to apply errata * The Cortex-A77 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs. * mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_cortex_a77 adr x0, wa_cve_vbar_cortex_a77
msr vbar_el3, x0 msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ #endif /* IMAGE_BL31 */
workaround_reset_end cortex_a77, CVE(2022, 23960)
#if ERRATA_A77_1800714 check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
mov x0, x18
bl errata_a77_1800714_wa
#endif
isb /* -------------------------------------------------
ret x19 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
endfunc cortex_a77_reset_func * -------------------------------------------------
*/
cpu_reset_func_start cortex_a77
cpu_reset_func_end cortex_a77
/* --------------------------------------------- /* ---------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -351,48 +158,16 @@ func cortex_a77_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_A77_CPUPWRCTLR_EL1, x0
#if ERRATA_A77_2743100 apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
mov x15, x30
bl cpu_get_rev_var
bl errata_a77_2743100_wa
mov x30, x15
#endif /* ERRATA_A77_2743100 */
isb isb
ret ret
endfunc cortex_a77_core_pwr_dwn endfunc cortex_a77_core_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_a77
/*
* Errata printing function for Cortex-A77. Must follow AAPCS.
*/
func cortex_a77_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
report_errata ERRATA_A77_1791578, cortex_a77, 1791578
report_errata ERRATA_A77_1800714, cortex_a77, 1800714
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
report_errata ERRATA_A77_1946167, cortex_a77, 1946167
report_errata ERRATA_A77_2356587, cortex_a77, 2356587
report_errata ERRATA_A77_2743100, cortex_a77, 2743100
report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a77_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex-A77 specific * This function provides Cortex-A77 specific
* register information for crash reporting. * register information for crash reporting.

220
lib/cpus/aarch64/cortex_a78_ae.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, ARM Limited. All rights reserved. * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -22,50 +22,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
/* -------------------------------------------------- workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
* Errata Workaround for A78 AE Erratum 1941500. sysreg_bit_clear CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
* This applies to revisions r0p0 and r0p1 of A78 AE. workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_ae_1941500_wa
/* Compare x0 against revisions r0p0 - r0p1 */
mov x17, x30
bl check_errata_1941500
cbz x0, 1f
/* Set bit 8 in ECTLR_EL1 */ check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1)
mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
msr CORTEX_A78_AE_CPUECTLR_EL1, x0
isb
1:
ret x17
endfunc errata_a78_ae_1941500_wa
func check_errata_1941500
/* Applies to revisions r0p0 and r0p1. */
mov x1, #CPU_REV(0, 0)
mov x2, #CPU_REV(0, 1)
b cpu_rev_var_range
endfunc check_errata_1941500
/* --------------------------------------------------
* Errata Workaround for A78 AE Erratum 1951502.
* This applies to revisions r0p0 and r0p1 of A78 AE.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_ae_1951502_wa
/* Compare x0 against revisions r0p0 - r0p1 */
mov x17, x30
bl check_errata_1951502
cbz x0, 1f
workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
msr S3_6_c15_c8_0, xzr msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002 ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0 msr S3_6_c15_c8_2, x0
@ -91,33 +54,11 @@ func errata_a78_ae_1951502_wa
msr S3_6_c15_c8_3, x0 msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0 msr S3_6_c15_c8_1, x0
workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
isb check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1)
1:
ret x17
endfunc errata_a78_ae_1951502_wa
func check_errata_1951502
/* Applies to revisions r0p0 and r0p1. */
mov x1, #CPU_REV(0, 0)
mov x2, #CPU_REV(0, 1)
b cpu_rev_var_range
endfunc check_errata_1951502
/* --------------------------------------------------
* Errata Workaround for A78 AE Erratum 2376748.
* This applies to revisions r0p0 and r0p1 of A78 AE.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_ae_2376748_wa
/* Compare x0 against revisions r0p0 - r0p1 */
mov x17, x30
bl check_errata_2376748
cbz x0, 1f
workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
/* ------------------------------------------------------- /* -------------------------------------------------------
* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to * Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
* behave like PLD/PRFM LD and not cause invalidations to * behave like PLD/PRFM LD and not cause invalidations to
@ -126,104 +67,42 @@ func errata_a78_ae_2376748_wa
* that share data. * that share data.
* ------------------------------------------------------- * -------------------------------------------------------
*/ */
mrs x0, CORTEX_A78_AE_ACTLR2_EL1 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0
orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0 workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
msr CORTEX_A78_AE_ACTLR2_EL1, x0
isb
1:
ret x17
endfunc errata_a78_ae_2376748_wa
func check_errata_2376748 check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 1)
/* Applies to revisions r0p0 and r0p1. */
mov x1, #CPU_REV(0, 0)
mov x2, #CPU_REV(0, 1)
b cpu_rev_var_range
endfunc check_errata_2376748
/* --------------------------------------------------
* Errata Workaround for A78 AE Erratum 2395408.
* This applies to revisions r0p0 and r0p1 of A78 AE.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_ae_2395408_wa
/* Compare x0 against revisions r0p0 - r0p1 */
mov x17, x30
bl check_errata_2395408
cbz x0, 1f
workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
/* -------------------------------------------------------- /* --------------------------------------------------------
* Disable folding of demand requests into older prefetches * Disable folding of demand requests into older prefetches
* with L2 miss requests outstanding by setting the * with L2 miss requests outstanding by setting the
* CPUACTLR2_EL1[40] to 1. * CPUACTLR2_EL1[40] to 1.
* -------------------------------------------------------- * --------------------------------------------------------
*/ */
mrs x0, CORTEX_A78_AE_ACTLR2_EL1 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40
orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40 workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
msr CORTEX_A78_AE_ACTLR2_EL1, x0
isb
1:
ret x17
endfunc errata_a78_ae_2395408_wa
func check_errata_2395408 check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1)
/* Applies to revisions r0p0 and r0p1. */
mov x1, #CPU_REV(0, 0)
mov x2, #CPU_REV(0, 1)
b cpu_rev_var_range
endfunc check_errata_2395408
func check_errata_cve_2022_23960 workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if WORKAROUND_CVE_2022_23960 #if IMAGE_BL31
mov x0, #ERRATA_APPLIES /*
#else * The Cortex-A78AE generic vectors are overridden to apply errata
mov x0, #ERRATA_MISSING * mitigation on exception entry from lower ELs.
#endif
ret
endfunc check_errata_cve_2022_23960
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78-AE
* -------------------------------------------------
*/ */
func cortex_a78_ae_reset_func override_vector_table wa_cve_vbar_cortex_a78_ae
mov x19, x30 #endif /* IMAGE_BL31 */
bl cpu_get_rev_var workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
mov x18, x0
#if ERRATA_A78_AE_1941500 check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
mov x0, x18
bl errata_a78_ae_1941500_wa
#endif
#if ERRATA_A78_AE_1951502
mov x0, x18
bl errata_a78_ae_1951502_wa
#endif
#if ERRATA_A78_AE_2376748
mov x0, x18
bl errata_a78_ae_2376748_wa
#endif
#if ERRATA_A78_AE_2395408
mov x0, x18
bl errata_a78_ae_2395408_wa
#endif
cpu_reset_func_start cortex_a78_ae
#if ENABLE_FEAT_AMU #if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3 sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el3, x0
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2 sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el2, x0
/* Enable group0 counters */ /* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@ -233,19 +112,7 @@ func cortex_a78_ae_reset_func
mov x0, #CORTEX_A78_AMU_GROUP1_MASK mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0 msr CPUAMCNTENSET1_EL0, x0
#endif #endif
cpu_reset_func_end cortex_a78_ae
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Cortex-A78AE generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_a78_ae
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret x19
endfunc cortex_a78_ae_reset_func
/* ------------------------------------------------------- /* -------------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -256,37 +123,12 @@ func cortex_a78_ae_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* ------------------------------------------------------- * -------------------------------------------------------
*/ */
mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_a78_ae_core_pwr_dwn endfunc cortex_a78_ae_core_pwr_dwn
/* errata_report_shim cortex_a78_ae
* Errata printing function for cortex_a78_ae. Must follow AAPCS.
*/
#if REPORT_ERRATA
func cortex_a78_ae_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408
report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a78_ae_errata_report
#endif
/* ------------------------------------------------------- /* -------------------------------------------------------
* This function provides cortex_a78_ae specific * This function provides cortex_a78_ae specific

82
lib/cpus/aarch64/denver.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -207,7 +207,14 @@ func denver_disable_dco
2: ret 2: ret
endfunc denver_disable_dco endfunc denver_disable_dco
func check_errata_cve_2017_5715 workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
#if IMAGE_BL31
adr x1, workaround_bpflush_runtime_exceptions
msr vbar_el3, x1
#endif
workaround_reset_end denver, CVE(2017, 5715)
check_erratum_custom_start denver, CVE(2017, 5715)
mov x0, #ERRATA_MISSING mov x0, #ERRATA_MISSING
#if WORKAROUND_CVE_2017_5715 #if WORKAROUND_CVE_2017_5715
/* /*
@ -224,43 +231,9 @@ func check_errata_cve_2017_5715
1: 1:
#endif #endif
ret ret
endfunc check_errata_cve_2017_5715 check_erratum_custom_end denver, CVE(2017, 5715)
func check_errata_cve_2018_3639 workaround_reset_start denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
/* -------------------------------------------------
* The CPU Ops reset function for Denver.
* -------------------------------------------------
*/
func denver_reset_func
mov x19, x30
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
/*
* Check if the CPU supports the special instruction
* required to flush the indirect branch predictor and
* RSB. Support for this operation can be determined by
* comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
*/
mrs x0, id_afr0_el1
mov x1, #0x10000
and x0, x0, x1
cmp x0, #0
adr x1, workaround_bpflush_runtime_exceptions
mrs x2, vbar_el3
csel x0, x1, x2, ne
msr vbar_el3, x0
#endif
#if WORKAROUND_CVE_2018_3639
/* /*
* Denver CPUs with DENVER_MIDR_PN3 or earlier, use different * Denver CPUs with DENVER_MIDR_PN3 or earlier, use different
* bits in the ACTLR_EL3 register to disable speculative * bits in the ACTLR_EL3 register to disable speculative
@ -277,8 +250,11 @@ func denver_reset_func
msr actlr_el3, x0 msr actlr_el3, x0
isb isb
dsb sy dsb sy
#endif workaround_reset_end denver, CVE(2018, 3639)
check_erratum_chosen denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
cpu_reset_func_start denver
/* ---------------------------------------------------- /* ----------------------------------------------------
* Reset ACTLR.PMSTATE to C1 state * Reset ACTLR.PMSTATE to C1 state
* ---------------------------------------------------- * ----------------------------------------------------
@ -293,9 +269,7 @@ func denver_reset_func
* ---------------------------------------------------- * ----------------------------------------------------
*/ */
bl denver_enable_dco bl denver_enable_dco
cpu_reset_func_end denver
ret x19
endfunc denver_reset_func
/* ---------------------------------------------------- /* ----------------------------------------------------
* The CPU Ops core power down function for Denver. * The CPU Ops core power down function for Denver.
@ -322,27 +296,7 @@ func denver_cluster_pwr_dwn
ret ret
endfunc denver_cluster_pwr_dwn endfunc denver_cluster_pwr_dwn
#if REPORT_ERRATA errata_report_shim denver
/*
* Errata printing function for Denver. Must follow AAPCS.
*/
func denver_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639
ldp x8, x30, [sp], #16
ret
endfunc denver_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Denver specific * This function provides Denver specific
@ -367,7 +321,7 @@ endfunc denver_cpu_reg_dump
.macro denver_cpu_ops_wa midr .macro denver_cpu_ops_wa midr
declare_cpu_ops_wa denver, \midr, \ declare_cpu_ops_wa denver, \midr, \
denver_reset_func, \ denver_reset_func, \
check_errata_cve_2017_5715, \ check_erratum_denver_5715, \
CPU_NO_EXTRA2_FUNC, \ CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \ CPU_NO_EXTRA3_FUNC, \
denver_core_pwr_dwn, \ denver_core_pwr_dwn, \