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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
feat(stm32mp2): add console configuration
Use UART driver and fill helpers for crash console. Add early console setup in bl2_el3_early_platform_setup(). Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ifb39554214dec05dafe4e306f8754e1454cdab61
This commit is contained in:
Yann Gautier
parent
4cfbb84aeb
commit
87a940e027
4 changed files with 188 additions and 1 deletions
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@ -5,15 +5,19 @@
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*/
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#include <asm_macros.S>
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#include <drivers/st/stm32_gpio.h>
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#include <platform_def.h>
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#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1)
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.globl platform_mem_init
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl plat_crash_console_init
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.globl plat_crash_console_flush
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.globl plat_crash_console_putc
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.globl plat_report_exception
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func platform_mem_init
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/* Nothing to do, don't need to init SYSRAM */
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@ -53,11 +57,138 @@ endfunc plat_is_my_cpu_primary
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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/* Reset UART peripheral */
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mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG)
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ldr x2, =DEBUG_UART_RST_BIT
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ldr x0, [x1]
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orr x0, x0, x2
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str x0, [x1]
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1:
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ldr x0, [x1]
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ands x2, x0, x2
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beq 1b
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bic x2, x2, #DEBUG_UART_RST_BIT
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str x2, [x1]
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2:
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ldr x0, [x1]
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ands x2, x0, x2
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bne 2b
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/* Enable GPIOs for UART TX */
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mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
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ldr w2, [x1]
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/* Configure GPIO */
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orr w2, w2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN
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str w2, [x1]
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mov_imm x1, DEBUG_UART_TX_GPIO_BANK_ADDRESS
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/* Set GPIO mode alternate */
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ldr w2, [x1, #GPIO_MODE_OFFSET]
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bic w2, w2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
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orr w2, w2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT)
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str w2, [x1, #GPIO_MODE_OFFSET]
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/* Set GPIO speed low */
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ldr w2, [x1, #GPIO_SPEED_OFFSET]
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bic w2, w2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT)
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str w2, [x1, #GPIO_SPEED_OFFSET]
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/* Set no-pull */
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ldr w2, [x1, #GPIO_PUPD_OFFSET]
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bic w2, w2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT)
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str w2, [x1, #GPIO_PUPD_OFFSET]
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/* Set alternate */
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#if DEBUG_UART_TX_GPIO_PORT >= GPIO_ALT_LOWER_LIMIT
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ldr w2, [x1, #GPIO_AFRH_OFFSET]
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bic w2, w2, #(GPIO_ALTERNATE_MASK << \
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((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
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orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << \
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((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
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str w2, [x1, #GPIO_AFRH_OFFSET]
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#else
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ldr w2, [x1, #GPIO_AFRL_OFFSET]
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bic w2, w2, #(GPIO_ALTERNATE_MASK << (DEBUG_UART_TX_GPIO_PORT << 2))
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orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << (DEBUG_UART_TX_GPIO_PORT << 2))
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str w2, [x1, #GPIO_AFRL_OFFSET]
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#endif
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/* Clear UART clock flexgen divisors, keep enable bit */
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mov_imm x1, (RCC_BASE + DEBUG_UART_PREDIV_CFGR)
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mov x2, #0
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str w2, [x1]
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mov_imm x1, (RCC_BASE + DEBUG_UART_FINDIV_CFGR)
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mov x2, #0x40
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str w2, [x1]
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/* Enable UART clock, with its source */
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mov_imm x1, (RCC_BASE + DEBUG_UART_TX_CLKSRC_REG)
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mov_imm w2, (DEBUG_UART_TX_CLKSRC | RCC_XBARxCFGR_XBARxEN)
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str w2, [x1]
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mov_imm x1, (RCC_BASE + DEBUG_UART_TX_EN_REG)
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ldr w2, [x1]
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orr w2, w2, #DEBUG_UART_TX_EN
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str w2, [x1]
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mov_imm x0, STM32MP_DEBUG_USART_BASE
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mov_imm x1, STM32MP_DEBUG_USART_CLK_FRQ
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mov_imm x2, STM32MP_UART_BAUDRATE
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b console_stm32_core_init
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endfunc plat_crash_console_init
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func plat_crash_console_flush
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mov_imm x0, STM32MP_DEBUG_USART_BASE
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b console_stm32_core_flush
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endfunc plat_crash_console_flush
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func plat_crash_console_putc
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mov_imm x1, STM32MP_DEBUG_USART_BASE
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cmp x0, #'\n'
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b.ne 1f
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mov x15, x30
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mov x0, #'\r'
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bl console_stm32_core_putc
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mov x30, x15
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mov x0, #'\n'
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1:
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b console_stm32_core_putc
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endfunc plat_crash_console_putc
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#ifdef IMAGE_BL2
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/* ---------------------------------------------
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* void plat_report_exception(unsigned int type)
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* Function to report an unhandled exception
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* with platform-specific means.
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* ---------------------------------------------
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*/
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func plat_report_exception
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mov x8, x30
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adr x4, plat_err_str
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bl asm_print_str
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adr x4, esr_el3_str
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bl asm_print_str
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mrs x4, esr_el3
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bl asm_print_hex
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adr x4, elr_el3_str
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bl asm_print_str
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mrs x4, elr_el3
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bl asm_print_hex
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adr x4, far_el3_str
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bl asm_print_str
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mrs x4, far_el3
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bl asm_print_hex
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mov x30, x8
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ret
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endfunc plat_report_exception
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.section .rodata.rev_err_str, "aS"
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plat_err_str:
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.asciz "\nPlatform exception reporting:"
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esr_el3_str:
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.asciz "\nESR_EL3: "
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elr_el3_str:
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.asciz "\nELR_EL3: "
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far_el3_str:
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.asciz "\nFAR_EL3: "
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#endif /* IMAGE_BL2 */
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@ -7,11 +7,14 @@
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#include <cdefs.h>
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#include <stdint.h>
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#include <stm32mp_common.h>
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void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
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u_register_t arg1 __unused,
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u_register_t arg2 __unused,
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u_register_t arg3 __unused)
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{
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stm32mp_setup_early_console();
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}
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void bl2_platform_setup(void)
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@ -34,7 +34,7 @@ TF_CFLAGS += -mbranch-protection=none
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PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
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PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
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PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
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PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
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BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
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@ -11,6 +11,7 @@
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#ifndef __ASSEMBLER__
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#include <drivers/st/bsec.h>
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#endif
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#include <drivers/st/stm32mp25_rcc.h>
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#include <dt-bindings/clock/stm32mp25-clks.h>
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#include <dt-bindings/clock/stm32mp25-clksrc.h>
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#include <dt-bindings/reset/stm32mp25-resets.h>
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@ -72,6 +73,58 @@ enum ddr_type {
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******************************************************************************/
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#define PWR_BASE U(0x44210000)
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/*******************************************************************************
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* STM32MP2 GPIO
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******************************************************************************/
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#define GPIOA_BASE U(0x44240000)
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#define GPIOB_BASE U(0x44250000)
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#define GPIOC_BASE U(0x44260000)
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#define GPIOD_BASE U(0x44270000)
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#define GPIOE_BASE U(0x44280000)
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#define GPIOF_BASE U(0x44290000)
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#define GPIOG_BASE U(0x442A0000)
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#define GPIOH_BASE U(0x442B0000)
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#define GPIOI_BASE U(0x442C0000)
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#define GPIOJ_BASE U(0x442D0000)
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#define GPIOK_BASE U(0x442E0000)
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#define GPIOZ_BASE U(0x46200000)
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#define GPIO_BANK_OFFSET U(0x10000)
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#define STM32MP_GPIOS_PIN_MAX_COUNT 16
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#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
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/*******************************************************************************
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* STM32MP2 UART
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******************************************************************************/
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#define USART1_BASE U(0x40330000)
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#define USART2_BASE U(0x400E0000)
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#define USART3_BASE U(0x400F0000)
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#define UART4_BASE U(0x40100000)
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#define UART5_BASE U(0x40110000)
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#define USART6_BASE U(0x40220000)
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#define UART7_BASE U(0x40370000)
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#define UART8_BASE U(0x40380000)
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#define UART9_BASE U(0x402C0000)
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#define STM32MP_NB_OF_UART U(9)
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/* For UART crash console */
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#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
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/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
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#define STM32MP_DEBUG_USART_BASE USART2_BASE
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#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
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#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
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#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
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#define DEBUG_UART_TX_GPIO_PORT 4
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#define DEBUG_UART_TX_GPIO_ALTERNATE 6
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#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
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#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
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#define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
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#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
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#define DEBUG_UART_RST_REG RCC_USART2CFGR
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#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
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#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
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#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
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/*******************************************************************************
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* STM32MP2 SDMMC
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******************************************************************************/
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