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Merge changes I814cdadb,I429eb473,I441f9a60 into integration

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* changes:
  fix(n1sdp): fix spi_ids range for n1sdp multichip boot
  fix(gicv3): move invocation of gicv3_get_multichip_base function
  fix(gic600): fix gic600 maximum SPI ID
This commit is contained in:
Manish V Badarkhe 2023-06-20 12:10:44 +02:00 • committed by TrustedFirmware Code Review
commit 8725938059
4 changed files with 11 additions and 8 deletions
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4
drivers/arm/gic/v3/gic600_multichip.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022-2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -217,7 +217,7 @@ static void gic600_multichip_validate_data(
/* SPI IDs range check */
if (!(spi_id_min >= GIC600_SPI_ID_MIN) ||
!(spi_id_max < GIC600_SPI_ID_MAX) ||
!(spi_id_max <= GIC600_SPI_ID_MAX) ||
!(spi_id_min <= spi_id_max) ||
!((spi_id_max - spi_id_min + 1) % 32 == 0)) {
ERROR("Invalid SPI IDs {%u, %u} passed for "

4
drivers/arm/gic/v3/gic600_multichip_private.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -39,7 +39,7 @@
/* SPI interrupt id minimum and maximum range */
#define GIC600_SPI_ID_MIN 32
#define GIC600_SPI_ID_MAX 960
#define GIC600_SPI_ID_MAX 991
#define GIC700_SPI_ID_MIN 32
#define GIC700_SPI_ID_MAX 991

7
drivers/arm/gic/v3/gicv3_helpers.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -223,13 +223,16 @@ unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
current_prop = &interrupt_props[i];
unsigned int intr_num = current_prop->intr_num;
uintptr_t multichip_gicd_base = gicv3_get_multichip_base(intr_num, gicd_base);
uintptr_t multichip_gicd_base;
/* Skip SGI, (E)PPI and LPI interrupts */
if (!IS_SPI(intr_num)) {
continue;
}
multichip_gicd_base =
gicv3_get_multichip_base(intr_num, gicd_base);
/* Configure this interrupt as a secure interrupt */
gicd_clr_igroupr(multichip_gicd_base, intr_num);

4
plat/arm/board/n1sdp/n1sdp_bl31_setup.c
View file

@ -52,8 +52,8 @@ static struct gic600_multichip_data n1sdp_multichip_data __init = {
PLAT_ARM_GICD_BASE >> 16
},
.spi_ids = {
{PLAT_ARM_GICD_BASE, 32, 479},
{PLAT_ARM_GICD_BASE, 512, 959}
{PLAT_ARM_GICD_BASE, 32, 511},
{PLAT_ARM_GICD_BASE, 512, 991}
}
};