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feat(fdts): add firewall regions into STM32MP1 DT

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Add the corresponding firewall memory regions
into fw-config device tree.

Change-Id: Ie39b0339f3c42b3dd756354138a872500c64f84c
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This commit is contained in:
Yann Gautier 2021-07-02 11:53:18 +02:00
parent 3cc5155c84
commit 86b43c58a4
1 changed files with 32 additions and 0 deletions
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32
fdts/stm32mp15-fw-config.dtsi
View file

@ -4,9 +4,27 @@
*/
#include <common/tbbr/tbbr_img_def.h>
#include <dt-bindings/soc/stm32mp15-tzc400.h>
#include <platform_def.h>
#ifndef DDR_SIZE
#error "DDR_SIZE is not defined"
#endif
#define DDR_NS_BASE STM32MP_DDR_BASE
#ifdef AARCH32_SP_OPTEE
/* OP-TEE reserved shared memory: located at DDR top */
#define DDR_SHARE_SIZE STM32MP_DDR_SHMEM_SIZE
#define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE))
/* OP-TEE secure memory: located right below OP-TEE reserved shared memory */
#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE
#define DDR_SEC_BASE (DDR_SHARE_BASE - DDR_SEC_SIZE)
#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE)
#else /* !AARCH32_SP_OPTEE */
#define DDR_NS_SIZE DDR_SIZE
#endif /* AARCH32_SP_OPTEE */
/dts-v1/;
/ {
@ -43,6 +61,20 @@
max-size = <STM32MP_BL32_DTB_SIZE>;
id = <TOS_FW_CONFIG_ID>;
};
#endif
};
st-mem-firewall {
compatible = "st,mem-firewall";
#ifdef AARCH32_SP_OPTEE
memory-ranges = <
DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR
DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0
DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)>;
#else
memory-ranges = <
DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>;
#endif
};
};