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feat(layerscape): add new soc errata a010539 support

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Add new soc errata a010539 support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Idbd8caaac12da8ab4f39dc0019cb656bcf4f3401
This commit is contained in:
Jiafei Pan 2022-02-18 18:32:18 +08:00
parent 785ee93cc3
commit 85bd092943
4 changed files with 37 additions and 1 deletions
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5
plat/nxp/common/soc_errata/errata.c
View file

@ -23,6 +23,11 @@ void soc_errata(void)
INFO("SoC workaround for Errata A009660 was applied\n");
erratum_a009660();
#endif
#if ERRATA_SOC_A010539
INFO("SoC workaround for Errata A010539 was applied\n");
erratum_a010539();
#endif
/*
* The following DDR Erratas workaround are implemented in DDR driver,
* but print information here.

3
plat/nxp/common/soc_errata/errata.mk
View file

@ -10,7 +10,8 @@
ERRATA := \
ERRATA_SOC_A050426 \
ERRATA_SOC_A008850 \
ERRATA_SOC_A009660
ERRATA_SOC_A009660 \
ERRATA_SOC_A010539
define enable_errata
$(1) ?= 0

26
plat/nxp/common/soc_errata/errata_a010539.c Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include <mmio.h>
#include <plat_common.h>
void erratum_a010539(void)
{
if (get_boot_dev() == BOOT_DEVICE_QSPI) {
unsigned int *porsr1 = (void *)(NXP_DCFG_ADDR +
DCFG_PORSR1_OFFSET);
uint32_t val;
val = (gur_in32(porsr1) & ~PORSR1_RCW_MASK);
mmio_write_32((uint32_t)(NXP_DCSR_DCFG_ADDR +
DCFG_DCSR_PORCR1_OFFSET), htobe32(val));
/* Erratum need to set '1' to all bits for reserved SCFG register 0x1a8 */
mmio_write_32((uint32_t)(NXP_SCFG_ADDR + 0x1a8),
htobe32(0xffffffff));
}
}

4
plat/nxp/common/soc_errata/errata_list.h
View file

@ -21,4 +21,8 @@ void erratum_a008850_post(void);
void erratum_a009660(void);
#endif
#ifdef ERRATA_SOC_A010539
void erratum_a010539(void);
#endif
#endif /* ERRATA_LIST_H */