From 85709f66194cef32377a32f8e153316648ebb4a9 Mon Sep 17 00:00:00 2001 From: Sona Mathew Date: Thu, 23 May 2024 16:04:30 -0500 Subject: [PATCH] fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1 Implements mitigation for CVE-2024-5660 that affects Neoverse-V1 revisions r0p0, r1p0, r1p1, r1p2. The workaround is to disable the hardware page aggregation at EL3 by setting CPUECTLR_EL1[46] = 1'b1. Public Documentation: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660 Change-Id: Ia59452ea38c66b291790956d7f2880bfcd56d45f Signed-off-by: Sona Mathew --- lib/cpus/aarch64/neoverse_v1.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 1ec3e944c..d1a2c24e9 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -26,6 +26,13 @@ wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 #endif /* WORKAROUND_CVE_2022_23960 */ +/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ +workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 + sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46) +workaround_reset_end neoverse_v1, CVE(2024, 5660) + +check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2) + workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635 /* Inserts a DMB SY before and after MRS PAR_EL1 */ ldr x0, =0x0