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Merge "fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32" into integration

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This commit is contained in:
Yann Gautier 2024-04-19 14:04:52 +02:00 • committed by TrustedFirmware Code Review
commit 85658c5695
2 changed files with 3 additions and 9 deletions
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6
lib/el3_runtime/aarch32/context_mgmt.c
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@ -149,11 +149,9 @@ static void enable_extensions_nonsecure(bool el2_unused)
trf_init_el3(); trf_init_el3();
} }
/* if (read_feat_pmuv3_id_field() >= 3U) {
* Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure
* state execution. This does not affect lower NS ELs.
*/
pmuv3_init_el3(); pmuv3_init_el3();
}
#endif /* IMAGE_BL32 */ #endif /* IMAGE_BL32 */
} }

4
lib/extensions/pmuv3/aarch32/pmuv3.c
View file

@ -25,10 +25,6 @@ static u_register_t mtpmu_disable_el3(u_register_t sdcr)
return sdcr; return sdcr;
} }
/*
* Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and
* to not clash with platforms which reuse the PMU name
*/
void pmuv3_init_el3(void) void pmuv3_init_el3(void)
{ {
u_register_t sdcr = read_sdcr(); u_register_t sdcr = read_sdcr();