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bl31: Add error reporting registers

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This patch adds cpumerrsr_el1 and l2merrsr_el1 to the register dump on
error for applicable CPUs.

These registers hold the ECC errors on L1 and L2 caches.

This patch updates the A53, A57, A72, A73 (l2merrsr_el1 only) CPU libraries.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
This commit is contained in:
Naga Sureshkumar Relli 2016-07-01 12:52:41 +05:30 • committed by Soren Brinkmann
parent 6f511c4782
commit 84629f2f2c
8 changed files with 46 additions and 4 deletions
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10
include/lib/cpus/aarch64/cortex_a53.h
View file

@ -56,6 +56,11 @@
#define CPUECTLR_FPU_RET_CTRL_SHIFT 3
#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
@ -79,4 +84,9 @@
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
#endif /* __CORTEX_A53_H__ */

10
include/lib/cpus/aarch64/cortex_a57.h
View file

@ -56,6 +56,11 @@
#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
@ -90,4 +95,9 @@
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
#endif /* __CORTEX_A57_H__ */

10
include/lib/cpus/aarch64/cortex_a72.h
View file

@ -44,6 +44,11 @@
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
@ -65,4 +70,9 @@
#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
#endif /* __CORTEX_A72_H__ */

5
include/lib/cpus/aarch64/cortex_a73.h
View file

@ -41,4 +41,9 @@
#define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
#endif /* __CORTEX_A73_H__ */

4
lib/cpus/aarch64/cortex_a53.S
View file

@ -234,11 +234,13 @@ endfunc cortex_a53_cluster_pwr_dwn
*/
.section .rodata.cortex_a53_regs, "aS"
cortex_a53_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
func cortex_a53_cpu_reg_dump
adr x6, cortex_a53_regs
mrs x8, CPUECTLR_EL1
mrs x9, CPUMERRSR_EL1
mrs x10, L2MERRSR_EL1
ret
endfunc cortex_a53_cpu_reg_dump

4
lib/cpus/aarch64/cortex_a57.S
View file

@ -477,11 +477,13 @@ endfunc cortex_a57_cluster_pwr_dwn
*/
.section .rodata.cortex_a57_regs, "aS"
cortex_a57_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
func cortex_a57_cpu_reg_dump
adr x6, cortex_a57_regs
mrs x8, CPUECTLR_EL1
mrs x9, CPUMERRSR_EL1
mrs x10, L2MERRSR_EL1
ret
endfunc cortex_a57_cpu_reg_dump

4
lib/cpus/aarch64/cortex_a72.S
View file

@ -231,11 +231,13 @@ endfunc cortex_a72_cluster_pwr_dwn
*/
.section .rodata.cortex_a72_regs, "aS"
cortex_a72_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
func cortex_a72_cpu_reg_dump
adr x6, cortex_a72_regs
mrs x8, CPUECTLR_EL1
mrs x9, CPUMERRSR_EL1
mrs x10, L2MERRSR_EL1
ret
endfunc cortex_a72_cpu_reg_dump

3
lib/cpus/aarch64/cortex_a73.S
View file

@ -144,11 +144,12 @@ endfunc cortex_a73_cluster_pwr_dwn
*/
.section .rodata.cortex_a73_regs, "aS"
cortex_a73_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
.asciz "cpuectlr_el1", "l2merrsr_el1", ""
func cortex_a73_cpu_reg_dump
adr x6, cortex_a73_regs
mrs x8, CORTEX_A73_CPUECTLR_EL1
mrs x9, CORTEX_A73_L2MERRSR_EL1
ret
endfunc cortex_a73_cpu_reg_dump