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rcar_gen3: drivers: watchdog
Signed-off-by: ldts <jramirez@baylibre.com>
This commit is contained in:
Jorge Ramirez-Ortiz
ldts
parent
33947f2e4f
commit
84433c5096
1 changed files with 158 additions and 0 deletions
158
drivers/renesas/rcar/watchdog/swdt.c
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158
drivers/renesas/rcar/watchdog/swdt.c
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <debug.h>
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#include <gicv2.h>
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#include <mmio.h>
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#include "rcar_def.h"
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extern void gicd_set_icenabler(uintptr_t base, unsigned int id);
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#define RST_BASE (0xE6160000U)
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#define RST_WDTRSTCR (RST_BASE + 0x0054U)
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#define SWDT_BASE (0xE6030000U)
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#define SWDT_WTCNT (SWDT_BASE + 0x0000U)
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#define SWDT_WTCSRA (SWDT_BASE + 0x0004U)
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#define SWDT_WTCSRB (SWDT_BASE + 0x0008U)
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#define SWDT_GICD_BASE (0xF1010000U)
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#define SWDT_GICC_BASE (0xF1020000U)
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#define SWDT_GICD_CTLR (SWDT_GICD_BASE + 0x0000U)
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#define SWDT_GICD_IGROUPR (SWDT_GICD_BASE + 0x0080U)
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#define SWDT_GICD_ISPRIORITYR (SWDT_GICD_BASE + 0x0400U)
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#define SWDT_GICC_CTLR (SWDT_GICC_BASE + 0x0000U)
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#define SWDT_GICC_PMR (SWDT_GICC_BASE + 0x0004U)
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#define SWDT_GICD_ITARGETSR (SWDT_GICD_BASE + 0x0800U)
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#define IGROUPR_NUM (16U)
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#define ISPRIORITY_NUM (128U)
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#define ITARGET_MASK (0x03U)
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#define WDTRSTCR_UPPER_BYTE (0xA55A0000U)
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#define WTCSRA_UPPER_BYTE (0xA5A5A500U)
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#define WTCSRB_UPPER_BYTE (0xA5A5A500U)
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#define WTCNT_UPPER_BYTE (0x5A5A0000U)
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#define WTCNT_RESET_VALUE (0xF488U)
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#define WTCSRA_BIT_CKS (0x0007U)
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#define WTCSRB_BIT_CKS (0x003FU)
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#define SWDT_RSTMSK (1U << 1U)
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#define WTCSRA_WOVFE (1U << 3U)
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#define WTCSRA_WRFLG (1U << 5U)
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#define SWDT_ENABLE (1U << 7U)
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#define WDTRSTCR_MASK_ALL (0x0000FFFFU)
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#define WTCSRA_MASK_ALL (0x000000FFU)
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#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE)
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#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU)
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#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U)
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#define WTCNT_COUNT_8p13k (0x10000U - 40687U)
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#define WTCNT_COUNT_8p13k_H3VER10 (0x10000U - 20343U)
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#define WTCNT_COUNT_8p22k (0x10000U - 41115U)
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#define WTCNT_COUNT_7p81k (0x10000U - 39062U)
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#define WTCSRA_CKS_DIV16 (0x00000002U)
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static void swdt_disable(void)
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{
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uint32_t rmsk;
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rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
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rmsk |= SWDT_RSTMSK;
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mmio_write_32(RST_WDTRSTCR, WDTRSTCR_UPPER_BYTE | rmsk);
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mmio_write_32(SWDT_WTCNT, WTCNT_INIT_DATA);
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mmio_write_32(SWDT_WTCSRA, WTCSRA_INIT_DATA);
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mmio_write_32(SWDT_WTCSRB, WTCSRB_INIT_DATA);
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/* Set the interrupt clear enable register */
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gicd_set_icenabler(RCAR_GICD_BASE, ARM_IRQ_SEC_WDT);
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}
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void rcar_swdt_init(void)
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{
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uint32_t rmsk, val, sr;
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#if (RCAR_LSI != RCAR_E3)
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uint32_t reg, product_cut, chk_data;
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reg = mmio_read_32(RCAR_PRR);
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product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
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reg = mmio_read_32(RCAR_MODEMR);
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chk_data = reg & CHECK_MD13_MD14;
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#endif
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/* stop watchdog */
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if (mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE)
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mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE);
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mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
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WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
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#if (RCAR_LSI == RCAR_E3)
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mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
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#else
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val = WTCNT_UPPER_BYTE;
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switch (chk_data) {
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case MD14_MD13_TYPE_0:
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case MD14_MD13_TYPE_2:
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val |= WTCNT_COUNT_8p13k;
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break;
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case MD14_MD13_TYPE_1:
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val |= WTCNT_COUNT_8p22k;
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break;
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case MD14_MD13_TYPE_3:
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val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ?
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WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
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break;
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default:
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ERROR("MODEMR ERROR value = %x\n", chk_data);
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panic();
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break;
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}
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mmio_write_32(SWDT_WTCNT, val);
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#endif
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rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
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rmsk |= SWDT_RSTMSK | WDTRSTCR_UPPER_BYTE;
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mmio_write_32(RST_WDTRSTCR, rmsk);
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while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U)
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;
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/* Start the System WatchDog Timer */
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sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL;
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mmio_write_32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE));
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}
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void rcar_swdt_release(void)
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{
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uintptr_t itarget = SWDT_GICD_ITARGETSR +
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(ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
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uint32_t i;
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write_daifset(DAIF_FIQ_BIT);
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swdt_disable();
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gicv2_cpuif_disable();
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for (i = 0; i < IGROUPR_NUM; i++)
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mmio_write_32(SWDT_GICD_IGROUPR + i * 4, 0U);
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for (i = 0; i < ISPRIORITY_NUM; i++)
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mmio_write_32(SWDT_GICD_ISPRIORITYR + i * 4, 0U);
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mmio_write_32(itarget, 0U);
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mmio_write_32(SWDT_GICD_CTLR, 0U);
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mmio_write_32(SWDT_GICC_CTLR, 0U);
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mmio_write_32(SWDT_GICC_PMR, 0U);
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}
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void rcar_swdt_exec(uint64_t p)
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{
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gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
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rcar_swdt_release();
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ERROR("\n");
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ERROR("System WDT overflow, occured address is %p\n", (void *)p);
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panic();
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}
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