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feat(fvp): add StandaloneMm manifest in fvp
Support StandaloneMm running with FF-A as S-EL0 SP
when TF-A is built with EL3 SPMC partition manager.
For this
1. add manifest file describing StandaloneMm partition.
2. add number of page mapping area.
3. StandaloneMm should use SRAM with 512K.
while enabling, StandaloneMm, BL1 image requires more size:
aarch64-none-elf/bin/ld: BL31 image has exceeded its limit.
aarch64-none-elf/bin/ld: region `RAM' overflowed by 16384 bytes
So, when using SRAM size with 512K configuration,
increase size limit of BL1 binary.
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Idaa1db510340ebb812cfd13588610b2eea941918
This commit is contained in:
Levi Yun
Yeoreum Yun
parent
9ae5f67306
commit
8416e7917f
2 changed files with 150 additions and 1 deletions
146
plat/arm/board/fvp/fdts/fvp_stmm_manifest.dts
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146
plat/arm/board/fvp/fdts/fvp_stmm_manifest.dts
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@ -0,0 +1,146 @@
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <platform_def.h>
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/ {
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#define MODE_SEL0 (0x1)
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#define MODE_SEL1 (0x2)
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#define SECURE_RO 0x1
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#define SECURE_RW 0x3
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#define SECURE_EXECUTE_RO 0x5
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#define SECURE_EXECUTE_RW 0x7
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#define NON_SECURE_RO 0x9
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#define NON_SECURE_RW 0xB
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#define NON_SECURE_EXECUTE_RO 0xD
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#define NON_SECURE_EXECUTE_RW 0xF
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/*
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* FF-A compatible Secure Partition Manager parses the
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* config file and fetch the following booting arguments to
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* pass on to the StandAloneMM(StMM) Secure Partition.
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*/
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compatible = "arm,ffa-manifest-1.0";
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description = "FVP Base StandaloneMm";
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ffa-version = <0x00010002>; /* 31:16 - Major, 15:0 - Minor */
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uuid = <0xdcae8d37 0x46446bf0 0xab401483 0xa3873c93>;
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id = <0x8001>;
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execution-ctx-count = <PLATFORM_CORE_COUNT>;
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exception-level = <MODE_SEL0>; /* SEL0*/
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execution-state = <0>; /* AArch64*/
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load-address = <0x0 0xff200000>;
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image-size = <0x0 0x00300000>;
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xlat-granule = <0>; /* 4KiB */
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boot-order = <0>;
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messaging-method = <0x603>; /* Direct req/resp/req2/resp2 supported. */
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gp-register-num = <0>;
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device-regions {
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compatible = "arm,ffa-manifest-device-regions";
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/**
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* System registers, rtc, uart and etc regions for access from S-EL0.
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*/
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io_fpga {
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base-address = <0x0 0x1C000000>;
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pages-count = <0x3000>;
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attributes = <SECURE_RW>;
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};
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system_reg_el0 {
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base-address = <0x0 0x1C010000>;
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pages-count = <0x10>;
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attributes = <SECURE_RW>;
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};
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/**
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* ARM CSS SoC Peripherals area.
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* Similar to SOC_CSS_MAP_DEVICE.
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*/
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soc_components {
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base-address = <0x0 0x20000000>;
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pages-count = <0xc200>;
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attributes = <SECURE_RO>;
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};
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/**
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* NOR0 Flash region, used for Firmware Image Update.
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*/
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nor_flash0 {
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base-address = <0x0 0x08000000>;
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pages-count = <0x4000>;
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attributes = <SECURE_RW>;
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};
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/**
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* NOR1 Flash region, used for Secure booting.
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*/
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nor_flash1 {
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base-address = <0x0 0x0c000000>;
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pages-count = <0x4000>;
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attributes = <SECURE_RW>;
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};
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};
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memory-regions {
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compatible = "arm,ffa-manifest-memory-regions";
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/*
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* SPM Payload memory. Mapped as code region for S-EL0
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* Similar to ARM_SP_IMAGE_MMAP.
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*/
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stmm_region {
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description = "image";
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base-address = <0x0 0xff200000>;
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pages-count = <0x300>;
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/* StMM will remap the regions during runtime */
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attributes = <SECURE_EXECUTE_RO>;
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};
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/*
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* Memory shared between EL3 and S-EL0.
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* Similar to ARM_SPM_BUF_EL0_MMAP.
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*/
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rx-tx-buffers {
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description = "shared-buff";
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base-address = <0x0 0xff500000>;
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pages-count = <0x100>;
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attributes = <SECURE_RW>;
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};
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/*
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* Memory shared between Normal world and S-EL0.
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* Similar to ARM_SP_IMAGE_NS_BUF_MMAP.
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*/
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ns_comm_buffer {
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/*
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* Description is needed for StMM to identify
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* ns-communication buffer.
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*/
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description = "ns-comm";
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base-address = <0x0 0xff600000>;
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pages-count = <0x10>;
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attributes = <NON_SECURE_RW>;
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};
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/*
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* Heap used by SP to allocate memory for DMA.
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*/
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heap {
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/*
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* Description is needed for StMM to identify
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* heap buffer.
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*/
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description = "heap";
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base-address = <0x0 0xFF610000>;
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pages-count = <0x7F0>;
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attributes = <SECURE_RW>;
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};
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};
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};
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@ -170,6 +170,8 @@
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# elif SPMC_AT_EL3
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# define PLAT_ARM_MMAP_ENTRIES 13
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# define MAX_XLAT_TABLES 11
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# define PLAT_SP_IMAGE_MMAP_REGIONS 30
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
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# else
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# define PLAT_ARM_MMAP_ENTRIES 9
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# if USE_DEBUGFS
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@ -220,7 +222,8 @@ defined(IMAGE_BL2) && MEASURED_BOOT
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* In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW
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* area.
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*/
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#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO
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#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \
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FVP_TRUSTED_SRAM_SIZE == 512
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#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000)
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#else
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#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
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