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feat(rme): add register definitions and helper functions for FEAT_RME
This patch adds new register and bit definitions for the Armv9-A Realm Management Extension (RME) as described in the Arm document DDI0615 (https://developer.arm.com/documentation/ddi0615/latest). The patch also adds TLB maintenance functions and a function to detect the presence of RME feature. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I03d2af7ea41a20a9e8a362a36b8099e3b4d18a11
This commit is contained in:
Zelalem Aweke
parent
fe82bcc04a
commit
81c272b3b7
4 changed files with 148 additions and 2 deletions
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@ -182,6 +182,11 @@
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#define ID_AA64PFR0_CSV2_SHIFT U(56)
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#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
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#define ID_AA64PFR0_CSV2_LENGTH U(4)
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#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
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#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
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#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
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#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
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#define ID_AA64PFR0_FEAT_RME_V1 U(1)
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/* Exception level handling */
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#define EL_IMPL_NONE ULL(0)
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@ -432,6 +437,9 @@
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/* SCR definitions */
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#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
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#define SCR_NSE_SHIFT U(62)
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#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
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#define SCR_GPF_BIT (UL(1) << 48)
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#define SCR_TWEDEL_SHIFT U(30)
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#define SCR_TWEDEL_MASK ULL(0xf)
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#define SCR_HXEn_BIT (UL(1) << 38)
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@ -1092,6 +1100,90 @@
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#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
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#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
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/*******************************************************************************
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* Realm management extension register definitions
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******************************************************************************/
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/* GPCCR_EL3 definitions */
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#define GPCCR_EL3 S3_6_C2_C1_6
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/* Least significant address bits protected by each entry in level 0 GPT */
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#define GPCCR_L0GPTSZ_SHIFT U(20)
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#define GPCCR_L0GPTSZ_MASK U(0xF)
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#define GPCCR_L0GPTSZ_30BITS U(0x0)
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#define GPCCR_L0GPTSZ_34BITS U(0x4)
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#define GPCCR_L0GPTSZ_36BITS U(0x6)
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#define GPCCR_L0GPTSZ_39BITS U(0x9)
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#define SET_GPCCR_L0GPTSZ(x) \
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((x & GPCCR_L0GPTSZ_MASK) << GPCCR_L0GPTSZ_SHIFT)
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/* Granule protection check priority bit definitions */
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#define GPCCR_GPCP_SHIFT U(17)
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#define GPCCR_GPCP_BIT (ULL(1) << GPCCR_EL3_GPCP_SHIFT)
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/* Granule protection check bit definitions */
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#define GPCCR_GPC_SHIFT U(16)
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#define GPCCR_GPC_BIT (ULL(1) << GPCCR_GPC_SHIFT)
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/* Physical granule size bit definitions */
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#define GPCCR_PGS_SHIFT U(14)
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#define GPCCR_PGS_MASK U(0x3)
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#define GPCCR_PGS_4K U(0x0)
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#define GPCCR_PGS_16K U(0x2)
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#define GPCCR_PGS_64K U(0x1)
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#define SET_GPCCR_PGS(x) \
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((x & GPCCR_PGS_MASK) << GPCCR_PGS_SHIFT)
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/* GPT fetch shareability attribute bit definitions */
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#define GPCCR_SH_SHIFT U(12)
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#define GPCCR_SH_MASK U(0x3)
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#define GPCCR_SH_NS U(0x0)
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#define GPCCR_SH_OS U(0x2)
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#define GPCCR_SH_IS U(0x3)
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#define SET_GPCCR_SH(x) \
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((x & GPCCR_SH_MASK) << GPCCR_SH_SHIFT)
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/* GPT fetch outer cacheability attribute bit definitions */
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#define GPCCR_ORGN_SHIFT U(10)
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#define GPCCR_ORGN_MASK U(0x3)
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#define GPCCR_ORGN_NC U(0x0)
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#define GPCCR_ORGN_WB_RA_WA U(0x1)
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#define GPCCR_ORGN_WT_RA_NWA U(0x2)
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#define GPCCR_ORGN_WB_RA_NWA U(0x3)
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#define SET_GPCCR_ORGN(x) \
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((x & GPCCR_ORGN_MASK) << GPCCR_ORGN_SHIFT)
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/* GPT fetch inner cacheability attribute bit definitions */
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#define GPCCR_IRGN_SHIFT U(8)
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#define GPCCR_IRGN_MASK U(0x3)
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#define GPCCR_IRGN_NC U(0x0)
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#define GPCCR_IRGN_WB_RA_WA U(0x1)
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#define GPCCR_IRGN_WT_RA_NWA U(0x2)
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#define GPCCR_IRGN_WB_RA_NWA U(0x3)
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#define SET_GPCCR_IRGN(x) \
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((x & GPCCR_IRGN_MASK) << GPCCR_IRGN_SHIFT)
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/* Protected physical address size bit definitions */
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#define GPCCR_PPS_SHIFT U(0)
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#define GPCCR_PPS_MASK U(0x7)
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#define GPCCR_PPS_4GB U(0x0)
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#define GPCCR_PPS_64GB U(0x1)
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#define GPCCR_PPS_1TB U(0x2)
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#define GPCCR_PPS_4TB U(0x3)
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#define GPCCR_PPS_16TB U(0x4)
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#define GPCCR_PPS_256TB U(0x5)
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#define GPCCR_PPS_4PB U(0x6)
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#define SET_GPCCR_PPS(x) \
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((x & GPCCR_PPS_MASK) << GPCCR_PPS_SHIFT)
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/* GPTBR_EL3 definitions */
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#define GPTBR_EL3 S3_6_C2_C1_4
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/* Base Address for the GPT bit definitions */
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#define GPTBR_BADDR_SHIFT U(0)
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#define GPTBR_BADDR_VAL_SHIFT U(12)
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#define GPTBR_BADDR_MASK ULL(0xffffffffff)
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/*******************************************************************************
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* RAS system registers
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******************************************************************************/
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@ -123,4 +123,15 @@ static inline bool is_feat_hcx_present(void)
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ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED);
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}
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static inline unsigned int get_armv9_2_feat_rme_support(void)
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{
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/*
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* Return the RME version, zero if not supported. This function can be
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* used as both an integer value for the RME version or compared to zero
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* to detect RME presence.
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*/
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return (unsigned int)(read_id_aa64pfr0_el1() >>
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ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
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}
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#endif /* ARCH_FEATURES_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -540,6 +540,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
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/* DynamIQ Shared Unit power management */
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DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
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/* Armv9.2 RME Registers */
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DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
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DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
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#define IS_IN_EL(x) \
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(GET_EL(read_CurrentEl()) == MODE_EL##x)
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@ -583,7 +587,28 @@ static inline uint64_t el_implemented(unsigned int el)
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}
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}
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/* Previously defined accesor functions with incomplete register names */
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/*
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* TLBIPAALLOS instruction
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* (TLB Inivalidate GPT Information by PA,
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* All Entries, Outer Shareable)
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*/
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static inline void tlbipaallos(void)
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{
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__asm__("SYS #6,c8,c1,#4");
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}
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/*
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* Invalidate cached copies of GPT entries
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* from TLBs by physical address
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*
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* @pa: the starting address for the range
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* of invalidation
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* @size: size of the range of invalidation
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*/
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void gpt_tlbi_by_pa(uint64_t pa, size_t size);
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/* Previously defined accessor functions with incomplete register names */
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#define read_current_el() read_CurrentEl()
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@ -15,6 +15,7 @@
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.globl zero_normalmem
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.globl zeromem
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.globl memcpy16
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.globl gpt_tlbi_by_pa
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.globl disable_mmu_el1
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.globl disable_mmu_el3
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@ -592,3 +593,20 @@ func fixup_gdt_reloc
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b.lo 1b
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ret
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endfunc fixup_gdt_reloc
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/*
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* TODO: Currently only supports size of 4KB,
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* support other sizes as well.
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*/
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func gpt_tlbi_by_pa
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#if ENABLE_ASSERTIONS
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cmp x1, #PAGE_SIZE_4KB
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ASM_ASSERT(eq)
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tst x0, #(PAGE_SIZE_MASK)
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ASM_ASSERT(eq)
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#endif
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lsr x0, x0, #FOUR_KB_SHIFT /* 4KB size encoding is zero */
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sys #6, c8, c4, #3, x0 /* TLBI RPAOS, <Xt> */
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dsb sy
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ret
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endfunc gpt_tlbi_by_pa
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