fix(errata): workaround for Cortex-A78C 2132064

Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.

This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2

docs/design/cpu-specific-build-macros.rst

@@ -325,6 +325,12 @@ For Cortex-A78 AE, the following errata build flags are defined :
   Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
   erratum is still open.
 
+For Cortex-A78C, the following errata build flags are defined :
+
+- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
+  Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
+  it is still open.
+
 For Cortex-X1 CPU, the following errata build flags are defined:
 
 - ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1

include/lib/cpus/aarch64/cortex_a78c.h

@@ -17,6 +17,8 @@
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
 #define CORTEX_A78C_CPUECTLR_EL1		        S3_0_C15_C1_4
+#define CORTEX_A78C_CPUECTLR_EL1_BIT6		        (ULL(1) << 6)
+#define CORTEX_A78C_CPUECTLR_EL1_BIT7		        (ULL(1) << 7)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

lib/cpus/aarch64/cortex_a78c.S

@@ -21,6 +21,43 @@
 	wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
 #endif /* WORKAROUND_CVE_2022_23960 */
 
+/* --------------------------------------------------
+ * Errata Workaround for A78C Erratum 2132064.
+ * This applies to revisions r0p1 and r0p2 of A78C
+ * and is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78c_2132064_wa
+	/* Compare x0 against revisions r0p0 - r0p1 */
+	mov	x17, x30
+	bl	check_errata_2132064
+	cbz	x0, 1f
+
+	/* --------------------------------------------------------
+	 * Place the data prefetcher in the most conservative mode
+	 * to reduce prefetches by writing the following bits to
+	 * the value indicated: ecltr[7:6], PF_MODE = 2'b11
+	 * --------------------------------------------------------
+	 */
+	mrs	x0, CORTEX_A78C_CPUECTLR_EL1
+	orr	x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT6
+	orr	x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT7
+	msr	CORTEX_A78C_CPUECTLR_EL1, x0
+	isb
+1:
+	ret	x17
+endfunc errata_a78c_2132064_wa
+
+func check_errata_2132064
+	/* Applies to revisions r0p1 and r0p2. */
+	mov	x1, #CPU_REV(0, 1)
+	mov	x2, #CPU_REV(0, 2)
+	b	cpu_rev_var_range
+endfunc check_errata_2132064
+
 func check_errata_cve_2022_23960
 #if WORKAROUND_CVE_2022_23960
 	mov	x0, #ERRATA_APPLIES
@@ -35,6 +72,15 @@ endfunc check_errata_cve_2022_23960
 	 * -------------------------------------------------
 	 */
 func cortex_a78c_reset_func
+	mov	x19, x30
+	bl	cpu_get_rev_var
+	mov	x18, x0
+
+#if ERRATA_A78C_2132064
+	mov	x0, x18
+	bl	errata_a78c_2132064_wa
+#endif
+
 #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
 	/*
 	 * The Cortex-A78c generic vectors are overridden to apply errata
@@ -43,8 +89,9 @@ func cortex_a78c_reset_func
 	adr	x0, wa_cve_vbar_cortex_a78c
 	msr	vbar_el3, x0
 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+
 	isb
-	ret
+	ret	x19
 endfunc cortex_a78c_reset_func
 
 	/* ----------------------------------------------------
@@ -77,6 +124,7 @@ func cortex_a78c_errata_report
 	 * Report all errata. The revision-variant information is passed to
 	 * checking functions of each errata.
 	 */
+	report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
 	report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
 
 	ldp	x8, x30, [sp], #16

lib/cpus/cpu-ops.mk

@@ -361,6 +361,10 @@ ERRATA_A78_AE_2376748	?=0
 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
 ERRATA_A78_AE_2395408	?=0
 
+# Flag to apply erratum 2132064 workaround during reset. This erratum applies
+# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
+ERRATA_A78C_2132064	?=0
+
 # Flag to apply erratum 1821534 workaround during reset. This erratum applies
 # to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
 ERRATA_X1_1821534	?=0
@@ -915,6 +919,10 @@ $(eval $(call add_define,ERRATA_A78_AE_2376748))
 $(eval $(call assert_boolean,ERRATA_A78_AE_2395408))
 $(eval $(call add_define,ERRATA_A78_AE_2395408))
 
+# Process ERRATA_A78C_2132064 flag
+$(eval $(call assert_boolean,ERRATA_A78C_2132064))
+$(eval $(call add_define,ERRATA_A78C_2132064))
+
 # Process ERRATA_X1_1821534 flag
 $(eval $(call assert_boolean,ERRATA_X1_1821534))
 $(eval $(call add_define,ERRATA_X1_1821534))