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fix(pmu): add sensible default for MDCR_EL2

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When TF-A is set to save and restore EL2 registers it initially zeroes
all of them so that it does not leak any information. However,
MDCR_EL2.HPMN of 0 is poorly defined when FEAT_HPMN0 is not implemented.
Set it to its hardware reset value so that lower ELs don't inherit a
wrong value.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8055005ef9b6eaafefa13b62a0b41289079fdd23
This commit is contained in:
Boyan Karatotev 2022-10-26 15:10:39 +01:00
parent 36d18c542e
commit 7f85619857
1 changed files with 10 additions and 0 deletions
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10
lib/el3_runtime/aarch64/context_mgmt.c
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@ -249,6 +249,16 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *
ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2,
icc_sre_el2);
/*
* Initialize MDCR_EL2.HPMN to its hardware reset value so we don't
* throw anyone off who expects this to be sensible.
* TODO: A similar thing happens in cm_prepare_el3_exit. They should be
* unified with the proper PMU implementation
*/
u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) &
PMCR_EL0_N_MASK);
write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2);
#endif /* CTX_INCLUDE_EL2_REGS */
}