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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-23 13:36:05 +00:00
uniphier: make all BL images completely position-independent
This platform supports multiple SoCs. The next SoC will still keep quite similar architecture, but the memory base will be changed. The ENABLE_PIE improves the maintainability and usability. You can reuse a single set of BL images for other SoC/board without re-compiling TF-A at all. This will also keep the code cleaner because it avoids #ifdef around various base addresses. By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really position-independent now. You can load them anywhere irrespective of their link address. Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
parent
c64873ab94
commit
7af2131787
6 changed files with 77 additions and 35 deletions
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@ -28,16 +28,36 @@
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_RET_STATE U(1)
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#define BL2_BASE ULL(0x80000000)
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#define UNIPHIER_BL2_OFFSET UL(0x00000000)
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#define BL2_LIMIT ULL(0x80080000)
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#define UNIPHIER_BL2_MAX_SIZE UL(0x00080000)
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/* 0x80080000-0x81000000: reserved for DSP */
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/* 0x00080000-0x01000000: reserved for DSP */
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#define BL31_BASE ULL(0x81000000)
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#define UNIPHIER_BL31_OFFSET UL(0x01000000)
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#define BL31_LIMIT ULL(0x81080000)
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#define UNIPHIER_BL31_MAX_SIZE UL(0x00080000)
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#define BL32_BASE ULL(0x81080000)
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#define UNIPHIER_BL32_OFFSET UL(0x01080000)
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#define BL32_LIMIT ULL(0x81180000)
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#define UNIPHIER_BL32_MAX_SIZE UL(0x00100000)
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/*
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* The link addresses are determined by UNIPHIER_MEM_BASE + offset.
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* When ENABLE_PIE is set, all the TF images can be loaded anywhere, so
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* UNIPHIER_MEM_BASE is arbitrary.
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*
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* When ENABLE_PIE is unset, UNIPHIER_MEM_BASE should be chosen so that
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* BL2_BASE matches to the physical address where BL2 is loaded, that is,
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* UNIPHIER_MEM_BASE should be the base address of the DRAM region.
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*/
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#define UNIPHIER_MEM_BASE UL(0x00000000)
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#define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET)
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#define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
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#define BL31_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL31_OFFSET)
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#define BL31_LIMIT (BL31_BASE + UNIPHIER_BL31_MAX_SIZE)
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#define BL32_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL32_OFFSET)
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#define BL32_LIMIT (BL32_BASE + UNIPHIER_BL32_MAX_SIZE)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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@ -9,6 +9,9 @@ override COLD_BOOT_SINGLE_CPU := 1
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override PROGRAMMABLE_RESET_ADDRESS := 1
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override PROGRAMMABLE_RESET_ADDRESS := 1
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override USE_COHERENT_MEM := 1
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override USE_COHERENT_MEM := 1
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override ENABLE_SVE_FOR_NS := 0
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override ENABLE_SVE_FOR_NS := 0
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# Disabling ENABLE_PIE saves memory footprint a lot, but you need to adjust
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# UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses.
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override ENABLE_PIE := 1
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override ENABLE_PIE := 1
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# Cortex-A53 revision r0p4-51rel0
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# Cortex-A53 revision r0p4-51rel0
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@ -42,8 +42,9 @@ int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec);
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int uniphier_usb_init(unsigned int soc,
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int uniphier_usb_init(unsigned int soc,
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struct io_block_dev_spec **block_dev_spec);
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struct io_block_dev_spec **block_dev_spec);
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int uniphier_io_setup(unsigned int soc);
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int uniphier_io_setup(unsigned int soc, uintptr_t mem_base);
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void uniphier_init_image_descs(uintptr_t mem_base);
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struct image_info;
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struct image_info;
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struct image_info *uniphier_get_image_info(unsigned int image_id);
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struct image_info *uniphier_get_image_info(unsigned int image_id);
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@ -67,11 +68,4 @@ void uniphier_gic_pcpu_init(void);
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unsigned int uniphier_calc_core_pos(u_register_t mpidr);
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unsigned int uniphier_calc_core_pos(u_register_t mpidr);
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#define UNIPHIER_BL33_BASE 0x84000000
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#define UNIPHIER_BL33_MAX_SIZE 0x00100000
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#define UNIPHIER_SCP_BASE ((UNIPHIER_BL33_BASE) + \
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(UNIPHIER_BL33_MAX_SIZE))
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#define UNIPHIER_SCP_MAX_SIZE 0x00020000
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#endif /* UNIPHIER_H */
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#endif /* UNIPHIER_H */
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@ -21,9 +21,10 @@
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#include "uniphier.h"
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#include "uniphier.h"
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#define UNIPHIER_IMAGE_BUF_BASE 0x84300000UL
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#define UNIPHIER_IMAGE_BUF_OFFSET 0x04300000UL
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#define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL
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#define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL
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static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE;
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static int uniphier_bl2_kick_scp;
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static int uniphier_bl2_kick_scp;
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void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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@ -41,13 +42,16 @@ void bl2_el3_plat_arch_setup(void)
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uniphier_mmap_setup();
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uniphier_mmap_setup();
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enable_mmu_el3(0);
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enable_mmu_el3(0);
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/* add relocation offset (run-time-address - link-address) */
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uniphier_mem_base += BL_CODE_BASE - BL2_BASE;
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soc = uniphier_get_soc_id();
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soc = uniphier_get_soc_id();
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if (soc == UNIPHIER_SOC_UNKNOWN) {
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if (soc == UNIPHIER_SOC_UNKNOWN) {
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ERROR("unsupported SoC\n");
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ERROR("unsupported SoC\n");
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plat_error_handler(-ENOTSUP);
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plat_error_handler(-ENOTSUP);
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}
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}
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ret = uniphier_io_setup(soc);
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ret = uniphier_io_setup(soc, uniphier_mem_base);
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if (ret) {
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if (ret) {
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ERROR("failed to setup io devices\n");
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ERROR("failed to setup io devices\n");
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plat_error_handler(ret);
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plat_error_handler(ret);
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@ -110,19 +114,19 @@ bl_params_t *plat_get_next_bl_params(void)
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void bl2_plat_preload_setup(void)
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void bl2_plat_preload_setup(void)
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{
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{
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#ifdef UNIPHIER_DECOMPRESS_GZIP
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#ifdef UNIPHIER_DECOMPRESS_GZIP
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uintptr_t buf_base = uniphier_mem_base + UNIPHIER_IMAGE_BUF_OFFSET;
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int ret;
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int ret;
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ret = mmap_add_dynamic_region(UNIPHIER_IMAGE_BUF_BASE,
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ret = mmap_add_dynamic_region(buf_base, buf_base,
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UNIPHIER_IMAGE_BUF_BASE,
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UNIPHIER_IMAGE_BUF_SIZE,
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UNIPHIER_IMAGE_BUF_SIZE,
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MT_MEMORY | MT_RW | MT_NS);
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MT_MEMORY | MT_RW | MT_NS);
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if (ret)
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if (ret)
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plat_error_handler(ret);
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plat_error_handler(ret);
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image_decompress_init(UNIPHIER_IMAGE_BUF_BASE,
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image_decompress_init(buf_base, UNIPHIER_IMAGE_BUF_SIZE, gunzip);
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UNIPHIER_IMAGE_BUF_SIZE,
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gunzip);
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#endif
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#endif
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uniphier_init_image_descs(uniphier_mem_base);
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}
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}
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int bl2_plat_handle_pre_image_load(unsigned int image_id)
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int bl2_plat_handle_pre_image_load(unsigned int image_id)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -13,13 +13,19 @@
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#include "uniphier.h"
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#include "uniphier.h"
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#define UNIPHIER_BL33_OFFSET 0x04000000UL
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#define UNIPHIER_BL33_MAX_SIZE 0x00100000UL
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#define UNIPHIER_SCP_OFFSET 0x04100000UL
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#define UNIPHIER_SCP_MAX_SIZE 0x00020000UL
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static struct bl_mem_params_node uniphier_image_descs[] = {
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static struct bl_mem_params_node uniphier_image_descs[] = {
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{
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{
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.image_id = SCP_BL2_IMAGE_ID,
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.image_id = SCP_BL2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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VERSION_2, image_info_t, 0),
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.image_info.image_base = UNIPHIER_SCP_BASE,
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.image_info.image_base = UNIPHIER_SCP_OFFSET,
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.image_info.image_max_size = UNIPHIER_SCP_MAX_SIZE,
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.image_info.image_max_size = UNIPHIER_SCP_MAX_SIZE,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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@ -33,13 +39,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = {
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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VERSION_2, image_info_t, 0),
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.image_info.image_base = BL31_BASE,
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.image_info.image_base = UNIPHIER_BL31_OFFSET,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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.image_info.image_max_size = UNIPHIER_BL31_MAX_SIZE,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.pc = UNIPHIER_BL31_OFFSET,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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VERSION_2, image_info_t, 0),
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.image_info.image_base = BL32_BASE,
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.image_info.image_base = UNIPHIER_BL32_OFFSET,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.image_info.image_max_size = UNIPHIER_BL32_MAX_SIZE,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE),
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SECURE | EXECUTABLE),
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.ep_info.pc = BL32_BASE,
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.ep_info.pc = UNIPHIER_BL32_OFFSET,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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DISABLE_ALL_EXCEPTIONS),
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@ -73,13 +79,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = {
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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VERSION_2, image_info_t, 0),
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.image_info.image_base = UNIPHIER_BL33_BASE,
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.image_info.image_base = UNIPHIER_BL33_OFFSET,
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.image_info.image_max_size = UNIPHIER_BL33_MAX_SIZE,
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.image_info.image_max_size = UNIPHIER_BL33_MAX_SIZE,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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VERSION_2, entry_point_info_t,
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NON_SECURE | EXECUTABLE),
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NON_SECURE | EXECUTABLE),
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.ep_info.pc = UNIPHIER_BL33_BASE,
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.ep_info.pc = UNIPHIER_BL33_OFFSET,
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.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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DISABLE_ALL_EXCEPTIONS),
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@ -88,6 +94,21 @@ static struct bl_mem_params_node uniphier_image_descs[] = {
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};
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};
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REGISTER_BL_IMAGE_DESCS(uniphier_image_descs)
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REGISTER_BL_IMAGE_DESCS(uniphier_image_descs)
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/*
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* image_info.image_base and ep_info.pc are the offset from the memory base.
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* When ENABLE_PIE is set, we never know the real memory base at link-time.
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* Fix-up the addresses by adding the run-time detected base.
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*/
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void uniphier_init_image_descs(uintptr_t mem_base)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(uniphier_image_descs); i++) {
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uniphier_image_descs[i].image_info.image_base += mem_base;
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uniphier_image_descs[i].ep_info.pc += mem_base;
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}
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}
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struct image_info *uniphier_get_image_info(unsigned int image_id)
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struct image_info *uniphier_get_image_info(unsigned int image_id)
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{
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{
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struct bl_mem_params_node *desc;
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struct bl_mem_params_node *desc;
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@ -26,7 +26,7 @@
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#define UNIPHIER_OCM_REGION_BASE 0x30000000ULL
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#define UNIPHIER_OCM_REGION_BASE 0x30000000ULL
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#define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL
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#define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL
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#define UNIPHIER_BLOCK_BUF_BASE 0x84200000UL
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#define UNIPHIER_BLOCK_BUF_OFFSET 0x04200000UL
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#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000UL
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#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000UL
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static const io_dev_connector_t *uniphier_fip_dev_con;
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static const io_dev_connector_t *uniphier_fip_dev_con;
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[UNIPHIER_BOOT_DEVICE_USB] = uniphier_io_usb_setup,
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[UNIPHIER_BOOT_DEVICE_USB] = uniphier_io_usb_setup,
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};
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};
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int uniphier_io_setup(unsigned int soc_id)
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int uniphier_io_setup(unsigned int soc_id, uintptr_t mem_base)
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{
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{
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int (*io_setup)(unsigned int soc_id, size_t buffer_offset);
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int (*io_setup)(unsigned int soc_id, size_t buffer_offset);
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unsigned int boot_dev;
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unsigned int boot_dev;
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return -EINVAL;
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return -EINVAL;
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io_setup = uniphier_io_setup_table[boot_dev];
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io_setup = uniphier_io_setup_table[boot_dev];
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ret = io_setup(soc_id, UNIPHIER_BLOCK_BUF_BASE);
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ret = io_setup(soc_id, mem_base + UNIPHIER_BLOCK_BUF_OFFSET);
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if (ret)
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if (ret)
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return ret;
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return ret;
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