Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-18 02:24:18 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge "plat/arm: Introduce A5 DesignStart platform." into integration

Browse source
This commit is contained in:
Soby Mathew 2019-07-17 09:38:51 +00:00 • committed by TrustedFirmware Code Review
commit 7a8ef89f97
14 changed files with 862 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

95
fdts/a5ds.dts Normal file
View file

@ -0,0 +1,95 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
model = "A5DS";
compatible = "arm,A5DS";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x7F000000>;
};
refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
smbclk: refclk24mhzx2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "smclk";
};
rtc@1a220000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x1a220000 0x1000>;
clocks = <&refclk100mhz>;
interrupts = <0 6 0xf04>;
clock-names = "apb_pclk";
};
gic: interrupt-controller@1c001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1c001000 0x1000>,
<0x1c000100 0x100>;
interrupts = <1 9 0xf04>;
};
serial0: uart@1a200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a200000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 8 0xf04>;
clocks = <&refclk100mhz>;
clock-names = "apb_pclk";
};
serial1: uart@1a210000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a210000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 9 0xf04>;
clocks = <&refclk100mhz>;
clock-names = "apb_pclk";
};
timer0: timer@1a040000 {
compatible = "arm,armv7-timer-mem";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x1a040000 0x1000>;
clock-frequency = <50000000>;
frame@1a050000 {
frame-number = <0>;
interrupts = <0 2 0xf04>;
reg = <0x1a050000 0x1000>;
};
};
};

20
plat/arm/board/a5ds/a5ds_bl1_setup.c Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*******************************************************************************
* Perform any BL1 specific platform actions.
******************************************************************************/
void bl1_early_platform_setup(void)
{
arm_bl1_early_platform_setup();
}
void bl1_platform_setup(void)
{
arm_bl1_platform_setup();
}

18
plat/arm/board/a5ds/a5ds_bl2_setup.c Normal file
View file

@ -0,0 +1,18 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
}
void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
}

56
plat/arm/board/a5ds/a5ds_common.c Normal file
View file

@ -0,0 +1,56 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <platform_def.h>
#include <plat/arm/common/arm_config.h>
#include <plat/arm/common/plat_arm.h>
#define MAP_PERIPHBASE MAP_REGION_FLAT(PERIPHBASE,\
PERIPH_SIZE,\
MT_DEVICE | MT_RW | MT_SECURE)
#define MAP_A5_PERIPHERALS MAP_REGION_FLAT(A5_PERIPHERALS_BASE,\
A5_PERIPHERALS_SIZE,\
MT_DEVICE | MT_RW | MT_SECURE)
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
{0}
};
#endif
#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
ARM_MAP_NS_DRAM1,
{0}
};
#endif
#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
{0}
};
#endif
ARM_CASSERT_MMAP
unsigned int plat_get_syscnt_freq2(void)
{
return A5DS_TIMER_BASE_FREQUENCY;
}

25
plat/arm/board/a5ds/a5ds_pm.c Normal file
View file

@ -0,0 +1,25 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/psci/psci.h>
#include <plat/arm/common/plat_arm.h>
/*******************************************************************************
* Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard
* platform layer will take care of registering the handlers with PSCI.
******************************************************************************/
plat_psci_ops_t a5ds_psci_pm_ops = {
/* dummy struct */
.validate_ns_entrypoint = NULL,
};
int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
*psci_ops = &a5ds_psci_pm_ops;
return 0;
}

15
plat/arm/board/a5ds/a5ds_private.h Normal file
View file

@ -0,0 +1,15 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef A5DS_PRIVATE_H
#define A5DS_PRIVATE_H
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void a5ds_config_setup(void);
#endif /* A5DS_PRIVATE_H */

17
plat/arm/board/a5ds/a5ds_security.c Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*
* We assume that all security programming is done by the primary core.
*/
void plat_arm_security_setup(void)
{
/*
* The platform currently does not have any security setup.
*/
}

53
plat/arm/board/a5ds/a5ds_topology.c Normal file
View file

@ -0,0 +1,53 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
/* The A5DS power domain tree descriptor */
static const unsigned char a5ds_power_domain_tree_desc[] = {
1,
/* No of children for the root node */
A5DS_CLUSTER_COUNT,
/* No of children for the first cluster node */
A5DS_CORE_COUNT,
};
/*******************************************************************************
* This function returns the topology according to A5DS_CLUSTER_COUNT.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return a5ds_power_domain_tree_desc;
}
/*******************************************************************************
* Get core position using mpidr
******************************************************************************/
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
unsigned int cluster_id, cpu_id;
mpidr &= MPIDR_AFFINITY_MASK;
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
return -1;
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
if (cluster_id >= A5DS_CLUSTER_COUNT)
return -1;
/*
* Validate cpu_id by checking whether it represents a CPU in
* one of the two clusters present on the platform.
*/
if (cpu_id >= A5DS_MAX_CPUS_PER_CLUSTER)
return -1;
return (cpu_id + (cluster_id * 4));
}

58
plat/arm/board/a5ds/aarch32/a5ds_helpers.S Normal file
View file

@ -0,0 +1,58 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <platform_def.h>
.globl plat_secondary_cold_boot_setup
.globl plat_get_my_entrypoint
.globl plat_is_my_cpu_primary
/* --------------------------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* For AArch32, cold-booting secondary CPUs is not yet
* implemented and they panic.
* --------------------------------------------------------------------
*/
func plat_secondary_cold_boot_setup
cb_panic:
wfi
b cb_panic
endfunc plat_secondary_cold_boot_setup
/* ---------------------------------------------------------------------
* unsigned long plat_get_my_entrypoint (void);
*
* Main job of this routine is to distinguish between a cold and warm
* boot.
* ---------------------------------------------------------------------
*/
func plat_get_my_entrypoint
/* TODO support warm boot */
/* Cold reset */
mov r0, #0
bx lr
endfunc plat_get_my_entrypoint
/* -----------------------------------------------------
* unsigned int plat_is_my_cpu_primary (void);
*
* Find out whether the current cpu is the primary
* cpu.
* -----------------------------------------------------
*/
func plat_is_my_cpu_primary
ldcopr r0, MPIDR
ldr r1, =MPIDR_AFFINITY_MASK
and r0, r1
cmp r0, #0
moveq r0, #1
movne r0, #0
bx lr
endfunc plat_is_my_cpu_primary

18
plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts Normal file
View file

@ -0,0 +1,18 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* Platform Config */
plat_arm_bl2 {
compatible = "arm,tb_fw";
hw_config_addr = <0x0 0x82000000>;
hw_config_max_size = <0x01000000>;
/* Disable authentication for development */
disable_auth = <0x0>;
};
};

350
plat/arm/board/a5ds/include/platform_def.h Normal file
View file

@ -0,0 +1,350 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <common/tbbr/tbbr_img_def.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/common/common_def.h>
/* Memory location options for TSP */
#define ARM_DRAM_ID 2
#define ARM_DRAM1_BASE UL(0x80000000)
#define ARM_DRAM1_SIZE UL(0x80000000)
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
/*
* The last 2MB is meant to be NOLOAD and will not be zero
* initialized.
*/
#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
0x00200000)
#define SRAM_BASE 0x2000000
#define SRAM_SIZE 0x200000
/* The first 4KB of NS DRAM1 are used as shared memory */
#define A5DS_SHARED_RAM_BASE SRAM_BASE
#define A5DS_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
/* The next 252 kB of NS DRAM is used to load the BL images */
#define ARM_BL_RAM_BASE (A5DS_SHARED_RAM_BASE + \
A5DS_SHARED_RAM_SIZE)
#define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \
A5DS_SHARED_RAM_SIZE)
#define PERIPHBASE 0x1a000000
#define PERIPH_SIZE 0x00240000
#define A5_PERIPHERALS_BASE 0x1c000000
#define A5_PERIPHERALS_SIZE 0x10000
#define ARM_CACHE_WRITEBACK_SHIFT 6
#define ARM_IRQ_SEC_PHY_TIMER 29
#define ARM_IRQ_SEC_SGI_0 8
#define ARM_IRQ_SEC_SGI_1 9
#define ARM_IRQ_SEC_SGI_2 10
#define ARM_IRQ_SEC_SGI_3 11
#define ARM_IRQ_SEC_SGI_4 12
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
/*
* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#define ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE)
#define ARM_G0_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE)
#define A5DS_IRQ_TZ_WDOG 56
#define A5DS_IRQ_SEC_SYS_TIMER 57
/* Default cluster count for A5DS */
#define A5DS_CLUSTER_COUNT 1
/* Default number of CPUs per cluster on A5DS */
#define A5DS_MAX_CPUS_PER_CLUSTER 4
/* Default number of threads per CPU on A5DS */
#define A5DS_MAX_PE_PER_CPU 1
#define A5DS_CORE_COUNT 1
#define A5DS_PRIMARY_CPU 0x0
#define FLASH1_BASE UL(0x8000000)
#define FLASH1_SIZE UL(0x2800000)
#define MAP_FLASH1_RW MAP_REGION_FLAT(FLASH1_BASE,\
FLASH1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define MAP_FLASH1_RO MAP_REGION_FLAT(FLASH1_BASE,\
FLASH1_SIZE, \
MT_RO_DATA | MT_SECURE)
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
A5DS_SHARED_RAM_BASE, \
A5DS_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
ARM_NS_DRAM1_BASE, \
ARM_NS_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define ARM_MAP_SRAM MAP_REGION_FLAT( \
SRAM_BASE, \
SRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
* Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
* share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
* in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
* to be able to access the heap.
*/
#define ARM_MAP_BL_RO MAP_REGION_FLAT(\
BL_CODE_BASE,\
BL_CODE_END - BL_CODE_BASE,\
MT_CODE | MT_SECURE),\
MAP_REGION_FLAT(\
BL_RO_DATA_BASE,\
BL_RO_DATA_END\
- BL_RO_DATA_BASE, \
MT_RO_DATA | MT_SECURE)
#if USE_COHERENT_MEM
#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT(\
BL_COHERENT_RAM_BASE,\
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 5
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)
/* Memory mapped Generic timer interfaces */
#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
#define ARM_CONSOLE_BAUDRATE 115200
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
/*
* This macro defines the deepest retention state possible. A higher state
* id will represent an invalid or a power down state.
*/
#define PLAT_MAX_RET_STATE 1
/*
* This macro defines the deepest power down states possible. Any state ID
* higher than this is invalid.
*/
#define PLAT_MAX_OFF_STATE 2
/*
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
*/
#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
/*
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space of BL2 meminfo.
*/
#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
#define BL1_RO_BASE 0x00000000
#define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE
/*
* Put BL1 RW at the top of the memory allocated for BL images in NS DRAM.
*/
#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE - \
(PLAT_ARM_MAX_BL1_RW_SIZE))
#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
(ARM_BL_RAM_SIZE))
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
/*
* Put BL2 just below BL1.
*/
#define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE)
#define BL2_LIMIT BL1_RW_BASE
/* Put BL32 below BL2 in NS DRAM.*/
#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT
#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
- PLAT_ARM_MAX_BL32_SIZE)
#define BL32_PROGBITS_LIMIT BL2_BASE
#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
/* Required platform porting definitions */
#define PLATFORM_CORE_COUNT 1
#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT) + 1
#define PLAT_MAX_PWR_LVL 2
/*
* Other platform porting definitions are provided by included headers
*/
/*
* Required ARM standard platform porting definitions
*/
#define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */
#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x10000 /* 64KB */
#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000)
/*
* Load address of BL33 for this platform port
*/
#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000))
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
#if defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 6
#else
# define PLAT_ARM_MMAP_ENTRIES 12
# define MAX_XLAT_TABLES 6
#endif
/*
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
* plus a little space for growth.
*/
#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
/*
* A5DS_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
* little space for growth.
*/
#define A5DS_MAX_BL2_SIZE 0x11000
/*
* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
#define PLAT_ARM_MAX_BL32_SIZE 0x3B000
/*
* Size of cacheable stacks
*/
#if defined(IMAGE_BL1)
# define PLATFORM_STACK_SIZE 0x440
#elif defined(IMAGE_BL2)
# define PLATFORM_STACK_SIZE 0x400
#elif defined(IMAGE_BL32)
# define PLATFORM_STACK_SIZE 0x440
#endif
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
#define PLAT_ARM_FIP_BASE FLASH1_BASE
#define PLAT_ARM_FIP_MAX_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_NVM_BASE FLASH1_BASE
#define PLAT_ARM_NVM_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
/*
* PL011 related constants
*/
#define PLAT_ARM_BOOT_UART_BASE 0x1A200000
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000
#define PLAT_ARM_RUN_UART_BASE 0x1A210000
#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
/* System timer related constants */
#define PLAT_ARM_NSTIMER_FRAME_ID 1
/* Mailbox base address */
#define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE
/*
* GIC related constants to cater for GICv2
*/
#define PLAT_ARM_GICD_BASE 0x1C001000
#define PLAT_ARM_GICC_BASE 0x1C000100
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(A5DS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(A5DS_IRQ_SEC_SYS_TIMER,\
GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
#endif /* PLATFORM_DEF_H */

94
plat/arm/board/a5ds/platform.mk Normal file
View file

@ -0,0 +1,94 @@
#
# Copyright (c) 2019, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Add `libfdt` and Arm common helpers required for Dynamic Config
include lib/libfdt/libfdt.mk
DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
plat/arm/common/arm_dyn_cfg_helpers.c \
common/fdt_wrappers.c
A5DS_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
A5DS_SECURITY_SOURCES := plat/arm/board/a5ds/a5ds_security.c
PLAT_INCLUDES := -Iplat/arm/board/a5ds/include
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/${ARCH}/pl011_console.S \
plat/arm/board/a5ds/a5ds_common.c \
plat/arm/common/${ARCH}/arm_helpers.S \
plat/arm/common/arm_common.c \
plat/arm/common/arm_console.c \
plat/arm/board/common/${ARCH}/board_arm_helpers.S
A5DS_CPU_LIBS := lib/cpus/aarch32/cortex_a5.S
BL1_SOURCES += drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
drivers/cfi/v2m/v2m_flash.c \
plat/arm/common/arm_bl1_setup.c \
plat/arm/common/arm_err.c \
plat/arm/common/arm_io_storage.c \
plat/arm/board/a5ds/${ARCH}/a5ds_helpers.S \
plat/arm/board/a5ds/a5ds_bl1_setup.c \
lib/aarch32/arm32_aeabi_divmod.c \
lib/aarch32/arm32_aeabi_divmod_a32.S \
${A5DS_CPU_LIBS} \
${DYN_CFG_SOURCES}
BL2_SOURCES += lib/aarch32/arm32_aeabi_divmod.c \
lib/aarch32/arm32_aeabi_divmod_a32.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/cfi/v2m/v2m_flash.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
plat/arm/board/a5ds/a5ds_bl2_setup.c \
plat/arm/common/arm_bl2_setup.c \
plat/arm/common/arm_err.c \
plat/arm/common/arm_io_storage.c \
plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \
plat/arm/common/arm_image_load.c \
common/desc_image_load.c \
${DYN_CFG_SOURCES} \
${A5DS_SECURITY_SOURCES}
# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
ifdef UNIX_MK
FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/a5ds_tb_fw_config.dtb
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config))
$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb, \
fdts/$(notdir ${FVP_HW_CONFIG_DTS})))
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config))
FDT_SOURCES += plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts \
${FVP_HW_CONFIG_DTS}
endif
NEED_BL32 := yes
MULTI_CONSOLE_API := 1
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c
# Use translation tables library v1 when using Cortex-A5
ARM_XLAT_TABLES_LIB_V1 := 1
$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG))
$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG))

22
plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c Normal file
View file

@ -0,0 +1,22 @@
/*
* Copyright (c) 2019, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
}
/*
* A5DS will only have one always-on power domain and there
* is no power control present.
*/
void plat_arm_pwrc_setup(void)
{
}

21
plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk Normal file
View file

@ -0,0 +1,21 @@
#
# Copyright (c) 2019, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# SP_MIN source files specific to A5DS platform
BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
lib/aarch32/arm32_aeabi_divmod.c \
lib/aarch32/arm32_aeabi_divmod_a32.S \
plat/arm/board/a5ds/aarch32/a5ds_helpers.S \
plat/arm/board/a5ds/a5ds_pm.c \
plat/arm/board/a5ds/a5ds_topology.c \
plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c \
plat/arm/common/sp_min/arm_sp_min_setup.c \
plat/common/aarch32/platform_mp_stack.S \
plat/common/plat_psci_common.c \
${A5DS_CPU_LIBS} \
${A5DS_GIC_SOURCES} \
${A5DS_SECURITY_SOURCES}