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Merge pull request #317 from vwadekar/run-bl32-on-tegra-v3

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Run bl32 on tegra v3
This commit is contained in:
Achin Gupta 2015-06-12 14:08:53 +01:00
commit 79b1ebdaae
5 changed files with 23 additions and 6 deletions
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11
docs/plat/nvidia-tegra.md
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@ -15,7 +15,16 @@ Directory structure
* plat/nvidia/tegra/common - Common code for all Tegra SoCs
* plat/nvidia/tegra/soc/txxx - Chip specific code
Trusted OS dispatcher
=====================
Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of
them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd'
on the command line while preparing a bl31 image. This allows other Trusted OS
vendors to use the upstream code and include their dispatchers in the image
without changing any makefiles.
Preparing the BL31 image to run on Tegra SoCs
===================================================
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
TARGET_SOC=<target-soc e.g. t210> all
TARGET_SOC=<target-soc e.g. t210> BL32=<path-to-trusted-os-binary> \
SPD=<dispatcher e.g. tlkd> all

0
docs/optee-dispatcher.md → docs/spd/optee-dispatcher.md
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5
docs/tlk-dispatcher.md → docs/spd/tlk-dispatcher.md
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@ -10,10 +10,11 @@ In order to compile TLK-D, we need a BL32 image to be present. Since, TLKD
just needs to compile, any BL32 image would do. To use TLK as the BL32, please
refer to the "Build TLK" section.
Once a BL32 is ready, TLKD can be compiled using the following command:
Once a BL32 is ready, TLKD can be included in the image using the following
command:
CROSS_COMPILE=<path_to_linaro_chain>/bin/aarch64-none-elf- make NEED_BL1=0
NEED_BL2=0 BL32=<path_to_BL32_image> PLAT=<platform> all
NEED_BL2=0 BL32=<path_to_BL32_image> PLAT=<platform> SPD=tlkd all
_
Trusted Little Kernel (TLK)
===========================

8
plat/nvidia/tegra/common/tegra_bl31_setup.c
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@ -82,7 +82,7 @@ extern uint64_t tegra_bl31_phys_base;
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
static entry_point_info_t bl33_image_ep_info;
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
(uint64_t)TZDRAM_SIZE, (uintptr_t)NULL
};
@ -102,6 +102,9 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
if (type == NON_SECURE)
return &bl33_image_ep_info;
if (type == SECURE)
return &bl32_image_ep_info;
return NULL;
}
@ -134,10 +137,11 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
plat_crash_console_init();
/*
* Copy BL3-3 entry point information.
* Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
bl33_image_ep_info = *from_bl2->bl33_ep_info;
bl32_image_ep_info = *from_bl2->bl32_ep_info;
/*
* Parse platform specific parameters - TZDRAM aperture size and

5
plat/nvidia/tegra/include/platform_def.h
View file

@ -69,8 +69,11 @@
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
#define BL31_SIZE 0x20000
#define BL31_BASE TZDRAM_BASE
#define BL31_LIMIT (TZDRAM_BASE + 0x11FFF)
#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
#define BL32_LIMIT TZDRAM_END
/*******************************************************************************
* Platform specific page table and MMU setup constants