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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge pull request #913 from vwadekar/tegra-fixes-from-downstream
Tegra fixes from downstream
This commit is contained in:
davidcunado-arm
GitHub
commit
798b084dee
9 changed files with 271 additions and 63 deletions
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@ -40,7 +40,8 @@
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#include <string.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <xlat_tables.h>
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#include <utils.h>
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#include <xlat_tables_v2.h>
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#define TEGRA_GPU_RESET_REG_OFFSET 0x30
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#define GPU_RESET_BIT (1 << 0)
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@ -450,7 +451,7 @@ void tegra_memctrl_restore_settings(void)
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb);
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/*
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* MCE propogates the VideoMem configuration values across the
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* MCE propagates the VideoMem configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_videomem();
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@ -490,7 +491,7 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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tegra_mc_read_32(MC_SECURITY_CFG1_0));
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/*
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* MCE propogates the security configuration values across the
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* MCE propagates the security configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_tzdram();
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@ -506,25 +507,28 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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uint32_t index;
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uint32_t total_128kb_blocks = size_in_bytes >> 17;
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uint32_t residual_4kb_blocks = (size_in_bytes & 0x1FFFF) >> 12;
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uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
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uint32_t val;
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INFO("Configuring TrustZone SRAM Memory Carveout\n");
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/*
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* Reset the access configuration registers to restrict access
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* to the TZRAM aperture
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*/
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for (index = MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0;
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index <= MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5;
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index += 4)
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for (index = MC_TZRAM_CLIENT_ACCESS_CFG0;
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index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
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index += 4U) {
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tegra_mc_write_32(index, 0);
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}
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/*
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* Set the TZRAM base. TZRAM base must be 4k aligned, at least.
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*/
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assert(!(phys_base & 0xFFF));
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assert((phys_base & (uint64_t)0xFFF) == 0U);
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tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_TZRAM_BASE_HI,
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(uint32_t)(phys_base >> 32) & TZRAM_BASE_HI_MASK);
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(uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
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/*
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* Set the TZRAM size
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@ -533,7 +537,7 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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* blocks)
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*
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*/
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val = (residual_4kb_blocks << TZRAM_SIZE_RANGE_4KB_SHIFT) |
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val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
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total_128kb_blocks;
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tegra_mc_write_32(MC_TZRAM_SIZE, val);
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@ -543,17 +547,96 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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* at all.
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*/
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val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
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val &= ~TZRAM_ENABLE_TZ_LOCK_BIT;
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val |= TZRAM_LOCK_CFG_SETTINGS_BIT;
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val &= ~MC_GSC_ENABLE_TZ_LOCK_BIT;
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val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
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tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
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/*
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* MCE propogates the security configuration values across the
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* MCE propagates the security configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_tzram();
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}
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static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
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uint64_t size_in_bytes)
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{
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uint32_t index;
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uint64_t total_128kb_blocks = size_in_bytes >> 17;
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uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
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uint64_t val;
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/*
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* Reset the access configuration registers to restrict access to
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* old Videomem aperture
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*/
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for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0;
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index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
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index += 4U) {
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tegra_mc_write_32(index, 0);
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}
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/*
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* Set the base. It must be 4k aligned, at least.
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*/
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assert((phys_base & (uint64_t)0xFFF) == 0U);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI,
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(uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK);
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/*
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* Set the aperture size
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*
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* total size = (number of 128KB blocks) + (number of remaining 4KB
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* blocks)
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*
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*/
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val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
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total_128kb_blocks);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val);
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/*
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* Lock the configuration settings by enabling TZ-only lock and
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* locking the configuration against any future changes from NS
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* world.
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*/
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG,
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(uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT);
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/*
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* MCE propagates the GSC configuration values across the
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* CCPLEX.
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*/
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}
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static void tegra_unlock_videomem_nonoverlap(void)
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{
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/* Clear the base */
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0);
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/* Clear the size */
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0);
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}
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static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
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unsigned long long non_overlap_area_size)
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{
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/*
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* Map the NS memory first, clean it and then unmap it.
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*/
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mmap_add_dynamic_region(non_overlap_area_start, /* PA */
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non_overlap_area_start, /* VA */
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non_overlap_area_size, /* size */
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MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
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zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
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flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
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mmap_remove_dynamic_region(non_overlap_area_start,
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non_overlap_area_size);
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}
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/*
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* Program the Video Memory carveout region
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*
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@ -562,7 +645,10 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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*/
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20);
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uintptr_t vmem_end_new = phys_base + size_in_bytes;
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uint32_t regval;
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unsigned long long non_overlap_area_size;
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/*
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* The GPU is the user of the Video Memory region. In order to
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@ -570,7 +656,7 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
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* new base/size ONLY if the GPU is in reset mode.
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*/
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regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
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if ((regval & GPU_RESET_BIT) == 0) {
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if ((regval & GPU_RESET_BIT) == 0U) {
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ERROR("GPU not in reset! Video Memory setup failed\n");
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return;
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}
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@ -581,17 +667,61 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
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*/
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INFO("Configuring Video Memory Carveout\n");
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/*
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* Configure Memory Controller directly for the first time.
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*/
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if (video_mem_base == 0U)
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goto done;
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/*
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* Lock the non overlapping memory being cleared so that other masters
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* do not accidently write to it. The memory would be unlocked once
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* the non overlapping region is cleared and the new memory
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* settings take effect.
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*/
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tegra_lock_videomem_nonoverlap(video_mem_base,
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video_mem_size_mb << 20);
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/*
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* Clear the old regions now being exposed. The following cases
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* can occur -
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*
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* 1. clear whole old region (no overlap with new region)
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* 2. clear old sub-region below new base
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* 3. clear old sub-region above new end
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*/
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INFO("Cleaning previous Video Memory Carveout\n");
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if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
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tegra_clear_videomem(video_mem_base,
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(uint64_t)video_mem_size_mb << 20);
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} else {
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if (video_mem_base < phys_base) {
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non_overlap_area_size = phys_base - video_mem_base;
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tegra_clear_videomem(video_mem_base, non_overlap_area_size);
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}
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if (vmem_end_old > vmem_end_new) {
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non_overlap_area_size = vmem_end_old - vmem_end_new;
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tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
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}
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}
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done:
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/* program the Videomem aperture */
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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(uint32_t)(phys_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
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/* unlock the previous locked nonoverlapping aperture */
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tegra_unlock_videomem_nonoverlap();
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/* store new values */
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video_mem_base = phys_base;
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video_mem_size_mb = size_in_bytes >> 20;
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/*
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* MCE propogates the VideoMem configuration values across the
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* MCE propagates the VideoMem configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_videomem();
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@ -204,6 +204,11 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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TEGRA_CONSOLE_BAUDRATE);
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}
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/*
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* Initialize delay timer
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*/
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tegra_delay_timer_init();
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/*
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* Do initial security configuration to allow DRAM/device access.
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*/
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@ -263,11 +268,6 @@ void bl31_platform_setup(void)
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/* Initialize the gic cpu and distributor interfaces */
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plat_gic_setup();
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/*
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* Initialize delay timer
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*/
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tegra_delay_timer_init();
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/*
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* Setup secondary CPU POR infrastructure.
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*/
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@ -354,6 +354,12 @@ void bl31_plat_arch_setup(void)
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* map on-chip free running uS timer */
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mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
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page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
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(uint64_t)TEGRA_TMRUS_SIZE,
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MT_DEVICE | MT_RO | MT_SECURE);
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/* add MMIO space */
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plat_mmio_map = plat_get_mmio_map();
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if (plat_mmio_map)
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@ -375,13 +381,12 @@ void bl31_plat_arch_setup(void)
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******************************************************************************/
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int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
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{
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uint64_t end = base + size_in_bytes - 1;
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uint64_t end = base + size_in_bytes;
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/*
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* Check if the NS DRAM address is valid
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*/
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if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) ||
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(base >= end)) {
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if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) {
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ERROR("NS address is out-of-bounds!\n");
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return -EFAULT;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -58,6 +58,7 @@
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x60005010
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#define TEGRA_TMRUS_SIZE 0x1000
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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@ -157,6 +157,16 @@
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#define TEGRA_MC_STREAMID_BASE 0x02C00000
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#define TEGRA_MC_BASE 0x02C10000
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/* General Security Carveout register macros */
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#define MC_GSC_CONFIG_REGS_SIZE 0x40UL
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#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1UL << 1)
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#define MC_GSC_ENABLE_TZ_LOCK_BIT (1UL << 0)
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#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27UL
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#define MC_GSC_BASE_LO_SHIFT 12UL
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#define MC_GSC_BASE_LO_MASK 0xFFFFFUL
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#define MC_GSC_BASE_HI_SHIFT 0UL
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#define MC_GSC_BASE_HI_MASK 3UL
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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@ -165,34 +175,24 @@
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64C
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/*
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* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
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* non-overlapping Video memory region
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*/
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#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0
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#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4
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#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8
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#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC
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#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0
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/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
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#define MC_TZRAM_CARVEOUT_CFG 0x2190
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#define MC_TZRAM_BASE_LO 0x2194
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#define TZRAM_BASE_LO_SHIFT 12
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#define TZRAM_BASE_LO_MASK 0xFFFFF
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#define MC_TZRAM_BASE_HI 0x2198
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#define TZRAM_BASE_HI_SHIFT 0
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#define TZRAM_BASE_HI_MASK 3
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#define MC_TZRAM_SIZE 0x219C
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#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
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#define MC_TZRAM_CARVEOUT_CFG 0x2190
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#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
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#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC
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#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0
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/*******************************************************************************
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* Tegra UART Controller constants
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@ -237,6 +237,7 @@
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* Tegra micro-seconds timer constants
|
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x0C2E0000
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#define TEGRA_TMRUS_SIZE 0x1000
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -83,6 +83,7 @@
|
|||
* Tegra micro-seconds timer constants
|
||||
******************************************************************************/
|
||||
#define TEGRA_TMRUS_BASE 0x60005010
|
||||
#define TEGRA_TMRUS_SIZE 0x1000
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra Clock and Reset Controller constants
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -30,10 +30,13 @@
|
|||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
#include <delay_timer.h>
|
||||
#include <denver.h>
|
||||
#include <mmio.h>
|
||||
#include <mce_private.h>
|
||||
#include <platform.h>
|
||||
#include <sys/errno.h>
|
||||
#include <t18x_ari.h>
|
||||
|
||||
|
|
@ -49,10 +52,13 @@
|
|||
#define ARI_RESPONSE_DATA_HI 0x18
|
||||
|
||||
/* Status values for the current request */
|
||||
#define ARI_REQ_PENDING 1
|
||||
#define ARI_REQ_ONGOING 3
|
||||
#define ARI_REQUEST_VALID_BIT (1 << 8)
|
||||
#define ARI_EVT_MASK_STANDBYWFI_BIT (1 << 7)
|
||||
#define ARI_REQ_PENDING 1U
|
||||
#define ARI_REQ_ONGOING 3U
|
||||
#define ARI_REQUEST_VALID_BIT (1U << 8)
|
||||
#define ARI_EVT_MASK_STANDBYWFI_BIT (1U << 7)
|
||||
|
||||
/* default timeout (ms) to wait for ARI completion */
|
||||
#define ARI_MAX_RETRY_COUNT 2000
|
||||
|
||||
/*******************************************************************************
|
||||
* ARI helper functions
|
||||
|
|
@ -96,7 +102,8 @@ static inline void ari_clobber_response(uint32_t ari_base)
|
|||
static int ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
|
||||
uint32_t lo, uint32_t hi)
|
||||
{
|
||||
int status;
|
||||
uint32_t retries = ARI_MAX_RETRY_COUNT;
|
||||
uint32_t status;
|
||||
|
||||
/* program the request, event_mask, hi and lo registers */
|
||||
ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO);
|
||||
|
|
@ -112,10 +119,36 @@ static int ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
|
|||
if (evt_mask)
|
||||
return 0;
|
||||
|
||||
/* NOTE: add timeout check if needed */
|
||||
status = ari_read_32(ari_base, ARI_STATUS);
|
||||
while (status & (ARI_REQ_ONGOING | ARI_REQ_PENDING))
|
||||
/* For shutdown/reboot commands, we dont have to check for timeouts */
|
||||
if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) &&
|
||||
((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
|
||||
(lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait for the command response for not more than the timeout
|
||||
*/
|
||||
while (retries != 0U) {
|
||||
|
||||
/* read the command status */
|
||||
status = ari_read_32(ari_base, ARI_STATUS);
|
||||
if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U)
|
||||
break;
|
||||
|
||||
/* delay 1 ms */
|
||||
mdelay(1);
|
||||
|
||||
/* decrement the retry count */
|
||||
retries--;
|
||||
}
|
||||
|
||||
/* assert if the command timed out */
|
||||
if (retries == 0U) {
|
||||
ERROR("ARI request timed out: req %d on CPU %d\n",
|
||||
req, plat_my_core_pos());
|
||||
assert(retries != 0U);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -188,8 +188,11 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
|||
int core_pos = read_mpidr() & MPIDR_CPU_MASK;
|
||||
mce_cstate_info_t cstate_info = { 0 };
|
||||
|
||||
/* get the current core's power state */
|
||||
target = *(states + core_pos);
|
||||
/* get the power state at this level */
|
||||
if (lvl == MPIDR_AFFLVL1)
|
||||
target = *(states + core_pos);
|
||||
if (lvl == MPIDR_AFFLVL2)
|
||||
target = *(states + cpu);
|
||||
|
||||
/* CPU suspend */
|
||||
if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) {
|
||||
|
|
@ -242,7 +245,8 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
|||
}
|
||||
|
||||
/* System Suspend */
|
||||
if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN))
|
||||
if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) &&
|
||||
(target == PSTATE_ID_SOC_POWERDN))
|
||||
return PSTATE_ID_SOC_POWERDN;
|
||||
|
||||
/* default state */
|
||||
|
|
|
|||
|
|
@ -100,6 +100,39 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
|||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform handler to calculate the proper target power level at the
|
||||
* specified affinity level
|
||||
******************************************************************************/
|
||||
plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||
const plat_local_state_t *states,
|
||||
unsigned int ncpu)
|
||||
{
|
||||
plat_local_state_t target = *states;
|
||||
int cpu = plat_my_core_pos();
|
||||
int core_pos = read_mpidr() & MPIDR_CPU_MASK;
|
||||
|
||||
/* get the power state at this level */
|
||||
if (lvl == MPIDR_AFFLVL1)
|
||||
target = *(states + core_pos);
|
||||
if (lvl == MPIDR_AFFLVL2)
|
||||
target = *(states + cpu);
|
||||
|
||||
/* Cluster idle/power-down */
|
||||
if ((lvl == MPIDR_AFFLVL1) && ((target == PSTATE_ID_CLUSTER_IDLE) ||
|
||||
(target == PSTATE_ID_CLUSTER_POWERDN))) {
|
||||
return target;
|
||||
}
|
||||
|
||||
/* System Suspend */
|
||||
if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) &&
|
||||
(target == PSTATE_ID_SOC_POWERDN))
|
||||
return PSTATE_ID_SOC_POWERDN;
|
||||
|
||||
/* default state */
|
||||
return PSCI_LOCAL_STATE_RUN;
|
||||
}
|
||||
|
||||
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
||||
{
|
||||
u_register_t mpidr = read_mpidr();
|
||||
|
|
@ -121,14 +154,14 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
|||
|
||||
} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) {
|
||||
|
||||
assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE);
|
||||
assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_IDLE);
|
||||
|
||||
/* Prepare for cluster idle */
|
||||
tegra_fc_cluster_idle(mpidr);
|
||||
|
||||
} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) {
|
||||
|
||||
assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE);
|
||||
assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_POWERDN);
|
||||
|
||||
/* Prepare for cluster powerdn */
|
||||
tegra_fc_cluster_powerdn(mpidr);
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
|
|||
PLATFORM_MAX_CPUS_PER_CLUSTER := 4
|
||||
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
MAX_XLAT_TABLES := 3
|
||||
MAX_XLAT_TABLES := 4
|
||||
$(eval $(call add_define,MAX_XLAT_TABLES))
|
||||
|
||||
MAX_MMAP_REGIONS := 8
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue