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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
This patch is used to implement 1. Cold/Warm reset and SMP support for Agilex5 SoC FPGA 2. Updated product name -> Agilex5 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d
This commit is contained in:
Jit Loon Lim
parent
9b8d813cc9
commit
79626f460f
3 changed files with 78 additions and 10 deletions
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@ -1,12 +1,14 @@
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/*
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* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#ifndef SOCFPGA_GIC_V3
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#ifndef GICV3_SUPPORT_GIC600
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#include <drivers/arm/gicv2.h>
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#else
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#include <drivers/arm/gicv3.h>
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@ -14,13 +16,16 @@
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include "socfpga_mailbox.h"
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#include "socfpga_plat_def.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_sip_svc.h"
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#include "socfpga_system_manager.h"
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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void socfpga_wakeup_secondary_cpu(unsigned int cpu_id);
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extern void plat_secondary_cold_boot_setup(void);
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#endif
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/*******************************************************************************
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* plat handler called when a CPU is about to enter standby.
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@ -43,13 +48,18 @@ void socfpga_cpu_standby(plat_local_state_t cpu_state)
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int socfpga_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/* TODO: Add in CPU FUSE from SDM */
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#else
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uint32_t psci_boot = 0x00;
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VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
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#endif
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if (cpu_id == -1)
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return PSCI_E_INTERN_FAIL;
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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if (cpu_id == 0x00) {
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psci_boot = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8));
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psci_boot |= 0x20000; /* bit 17 */
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@ -57,9 +67,16 @@ int socfpga_pwr_domain_on(u_register_t mpidr)
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}
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mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
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#endif
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/* release core reset */
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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bl31_plat_set_secondary_cpu_entrypoint(cpu_id);
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#else
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mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
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mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
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#endif
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return PSCI_E_SUCCESS;
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}
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@ -74,7 +91,12 @@ void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
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__func__, i, target_state->pwr_domain_state[i]);
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/* Prevent interrupts from spuriously waking up this cpu */
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#ifdef GICV3_SUPPORT_GIC600
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gicv3_cpuif_disable(plat_my_core_pos());
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#else
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gicv2_cpuif_disable();
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#endif
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}
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/*******************************************************************************
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@ -83,15 +105,18 @@ void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
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******************************************************************************/
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void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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unsigned int cpu_id = plat_my_core_pos();
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#endif
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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/* assert core reset */
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mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
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#endif
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}
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/*******************************************************************************
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@ -105,12 +130,18 @@ void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* Enable the gic cpu interface */
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#ifdef GICV3_SUPPORT_GIC600
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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#else
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/* Program the gic per-cpu distributor or re-distributor interface */
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gicv2_pcpu_distif_init();
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gicv2_set_pe_target_mask(plat_my_core_pos());
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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#endif
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}
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/*******************************************************************************
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@ -122,14 +153,18 @@ void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
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******************************************************************************/
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void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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unsigned int cpu_id = plat_my_core_pos();
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#endif
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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/* release core reset */
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mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
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#endif
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}
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/*******************************************************************************
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@ -163,11 +198,20 @@ static void __dead2 socfpga_system_reset(void)
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static int socfpga_system_reset2(int is_vendor, int reset_type,
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u_register_t cookie)
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{
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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mailbox_reset_warm(reset_type);
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#else
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if (cold_reset_for_ecc_dbe()) {
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mailbox_reset_cold();
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}
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#endif
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/* disable cpuif */
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#ifdef GICV3_SUPPORT_GIC600
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gicv3_cpuif_disable(plat_my_core_pos());
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#else
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gicv2_cpuif_disable();
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#endif
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/* Store magic number */
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mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
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@ -178,8 +222,10 @@ static int socfpga_system_reset2(int is_vendor, int reset_type,
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/* Enable handshakes */
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET);
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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/* Reset L2 module */
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mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100);
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#endif
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while (1)
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wfi();
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@ -9,10 +9,13 @@
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#include <assert.h>
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#include <common/debug.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/cadence/cdns_nand.h>
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#include <drivers/cadence/cdns_sdmmc.h>
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#include <drivers/io/io_block.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_fip.h>
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#include <drivers/io/io_memmap.h>
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#include <drivers/io/io_mtd.h>
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#include <drivers/io/io_storage.h>
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#include <drivers/mmc.h>
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#include <drivers/partition/partition.h>
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@ -21,17 +24,21 @@
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#include "socfpga_private.h"
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#define PLAT_FIP_BASE (0)
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#define PLAT_FIP_MAX_SIZE (0x1000000)
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#define PLAT_MMC_DATA_BASE (0xffe3c000)
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#define PLAT_MMC_DATA_SIZE (0x2000)
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#define PLAT_QSPI_DATA_BASE (0x3C00000)
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#define PLAT_QSPI_DATA_SIZE (0x1000000)
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#define PLAT_NAND_DATA_BASE (0x0200000)
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#define PLAT_NAND_DATA_SIZE (0x1000000)
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static const io_dev_connector_t *fip_dev_con;
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static const io_dev_connector_t *boot_dev_con;
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static io_mtd_dev_spec_t nand_dev_spec;
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static uintptr_t fip_dev_handle;
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static uintptr_t boot_dev_handle;
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@ -136,7 +143,7 @@ void socfpga_io_setup(int boot_source)
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case BOOT_SOURCE_SDMMC:
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register_io_dev = ®ister_io_dev_block;
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boot_dev_spec.buffer.offset = PLAT_MMC_DATA_BASE;
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boot_dev_spec.buffer.length = MMC_BLOCK_SIZE;
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boot_dev_spec.buffer.length = SOCFPGA_MMC_BLOCK_SIZE;
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boot_dev_spec.ops.read = mmc_read_blocks;
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boot_dev_spec.ops.write = mmc_write_blocks;
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boot_dev_spec.block_size = MMC_BLOCK_SIZE;
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@ -144,9 +151,19 @@ void socfpga_io_setup(int boot_source)
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case BOOT_SOURCE_QSPI:
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register_io_dev = ®ister_io_dev_memmap;
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fip_spec.offset = fip_spec.offset + PLAT_QSPI_DATA_BASE;
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fip_spec.offset = PLAT_QSPI_DATA_BASE;
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break;
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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case BOOT_SOURCE_NAND:
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register_io_dev = ®ister_io_dev_mtd;
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nand_dev_spec.ops.init = cdns_nand_init_mtd;
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nand_dev_spec.ops.read = cdns_nand_read;
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nand_dev_spec.ops.write = NULL;
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fip_spec.offset = PLAT_NAND_DATA_BASE;
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break;
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#endif
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default:
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ERROR("Unsupported boot source\n");
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panic();
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@ -159,8 +176,13 @@ void socfpga_io_setup(int boot_source)
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result = register_io_dev_fip(&fip_dev_con);
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assert(result == 0);
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if (boot_source == BOOT_SOURCE_NAND) {
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result = io_dev_open(boot_dev_con, (uintptr_t)&nand_dev_spec,
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&boot_dev_handle);
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} else {
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result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec,
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&boot_dev_handle);
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}
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assert(result == 0);
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result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
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@ -33,8 +33,8 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
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return -1;
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
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cluster_id = (mpidr >> PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> PLAT_CPU_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK;
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if (cluster_id >= PLATFORM_CLUSTER_COUNT)
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return -1;
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