Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-27 23:35:10 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge changes I58ba6b70,Id463a9dd into integration

Browse source 
* changes:
  fix(tc): set console baurate to 38400 for fvp as well
  refactor(tc): remove redundant macro UARTCLK_FREQ
This commit is contained in:
Manish Pandey 2025-01-08 12:57:23 +01:00 • committed by TrustedFirmware Code Review
commit 78f9c43786
4 changed files with 9 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
fdts/tc-base.dtsi
View file

@ -387,7 +387,7 @@
soc_uartclk: uartclk { soc_uartclk: uartclk {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <UARTCLK_FREQ>; clock-frequency = <TC_UARTCLK>;
clock-output-names = "uartclk"; clock-output-names = "uartclk";
}; };

1
fdts/tc2.dts
View file

@ -36,7 +36,6 @@
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu" #define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ #define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
#define DPU_ADDR 2cc00000 #define DPU_ADDR 2cc00000
#define DPU_IRQ 69 #define DPU_IRQ 69

1
fdts/tc3-4-base.dtsi
View file

@ -18,7 +18,6 @@
#define MHU_RX_INT_NAME "combined" #define MHU_RX_INT_NAME "combined"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ #define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP #if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000 #define DPU_ADDR 4000000000

15
plat/arm/board/tc/include/platform_def.h
View file

@ -443,18 +443,19 @@
#undef PLAT_ARM_BOOT_UART_CLK_IN_HZ #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ
#undef PLAT_ARM_RUN_UART_CLK_IN_HZ #undef PLAT_ARM_RUN_UART_CLK_IN_HZ
#if TARGET_FLAVOUR_FVP #undef ARM_CONSOLE_BAUDRATE
#define PLAT_ARM_BOOT_UART_BASE TC_UART1 #define ARM_CONSOLE_BAUDRATE 38400
#define TC_UARTCLK 7372800
#else /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_BOOT_UART_BASE TC_UART0
#if TARGET_PLATFORM <= 2 #if TARGET_PLATFORM <= 2
#define TC_UARTCLK 5000000 #define TC_UARTCLK 5000000
#elif TARGET_PLATFORM >= 3 #elif TARGET_PLATFORM >= 3
#define TC_UARTCLK 3750000 #define TC_UARTCLK 3750000
#endif /* TARGET_PLATFORM >= 3 */ #endif /* TARGET_PLATFORM >= 3 */
#undef ARM_CONSOLE_BAUDRATE
#define ARM_CONSOLE_BAUDRATE 38400 #if TARGET_FLAVOUR_FVP
#define PLAT_ARM_BOOT_UART_BASE TC_UART1
#else /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_BOOT_UART_BASE TC_UART0
#endif /* TARGET_FLAVOUR_FPGA */ #endif /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_RUN_UART_BASE TC_UART0 #define PLAT_ARM_RUN_UART_BASE TC_UART0