mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
Fix GICv3 DT to include psci system off/reset
The `fvp-base-gicv3-psci` and `fvp-foundation-gicv3-psci` device tree source files did not have psci node entries for `system off` and `system reset`. Also the DTS files included `rtsm_ve-motherboard-no_psci.dtsi` instead of `rtsm_ve-motherboard.dtsi`. As a result, the Linux kernel failed to invoke the PSCI_SYSTEM_OFF/RESET API when being shutdown/reset. This patch corrects this problem and also updates the corresponding DTB files. This patch also removes `rtsm_ve-motherboard-no_psci.dtsi` and `fvp-foundation-motherboard-no_psci.dtsi` files as they are no longer used. Change-Id: I8ba61a1323035f7508cae663bb490ac0e8a64618
This commit is contained in:
Soby Mathew
parent
a5a4231008
commit
78c4f19293
6 changed files with 6 additions and 463 deletions
Binary file not shown.
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@ -57,6 +57,8 @@
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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};
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cpus {
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@ -310,7 +312,7 @@
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<0 0 41 &gic 0 0 0 41 4>,
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<0 0 42 &gic 0 0 0 42 4>;
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/include/ "rtsm_ve-motherboard-no_psci.dtsi"
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/include/ "rtsm_ve-motherboard.dtsi"
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};
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panels {
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@ -57,6 +57,8 @@
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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};
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cpus {
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@ -259,6 +261,6 @@
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<0 0 41 &gic 0 0 0 41 4>,
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<0 0 42 &gic 0 0 0 42 4>;
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/include/ "fvp-foundation-motherboard-no_psci.dtsi"
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/include/ "fvp-foundation-motherboard.dtsi"
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};
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};
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@ -1,197 +0,0 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of the ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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motherboard {
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arm,v2m-memory-map = "rs1";
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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ranges;
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ethernet@2,02000000 {
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compatible = "smsc,lan91c111";
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reg = <2 0x02000000 0x10000>;
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interrupts = <15>;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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iofpga@3,00000000 {
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compatible = "arm,amba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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v2m_sysreg: sysreg@010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x010000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_sysctl: sysctl@020000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x020000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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};
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v2m_serial0: uart@090000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x090000 0x1000>;
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interrupts = <5>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@0a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <6>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: uart@0b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b0000 0x1000>;
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interrupts = <7>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: uart@0c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c0000 0x1000>;
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interrupts = <8>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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wdt@0f0000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f0000 0x1000>;
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interrupts = <0>;
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clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
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clock-names = "wdogclk", "apb_pclk";
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};
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v2m_timer01: timer@110000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x110000 0x1000>;
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interrupts = <2>;
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clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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v2m_timer23: timer@120000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x120000 0x1000>;
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interrupts = <3>;
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clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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rtc@170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x170000 0x1000>;
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interrupts = <4>;
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clocks = <&v2m_clk24mhz>;
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clock-names = "apb_pclk";
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};
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virtio_block@0130000 {
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compatible = "virtio,mmio";
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reg = <0x130000 0x1000>;
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interrupts = <0x2a>;
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};
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};
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v2m_fixed_3v3: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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mcc {
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compatible = "arm,vexpress,config-bus", "simple-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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reset@0 {
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compatible = "arm,vexpress-reset";
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arm,vexpress-sysreg,func = <5 0>;
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};
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muxfpga@0 {
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compatible = "arm,vexpress-muxfpga";
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arm,vexpress-sysreg,func = <7 0>;
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};
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shutdown@0 {
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compatible = "arm,vexpress-shutdown";
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arm,vexpress-sysreg,func = <8 0>;
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};
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reboot@0 {
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compatible = "arm,vexpress-reboot";
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arm,vexpress-sysreg,func = <9 0>;
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};
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dvimode@0 {
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compatible = "arm,vexpress-dvimode";
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arm,vexpress-sysreg,func = <11 0>;
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};
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};
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};
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@ -1,264 +0,0 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
|
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* to endorse or promote products derived from this software without specific
|
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* prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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motherboard {
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arm,v2m-memory-map = "rs1";
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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ranges;
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flash@0,00000000 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<4 0x00000000 0x04000000>;
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bank-width = <4>;
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};
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vram@2,00000000 {
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compatible = "arm,vexpress-vram";
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reg = <2 0x00000000 0x00800000>;
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};
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ethernet@2,02000000 {
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compatible = "smsc,lan91c111";
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reg = <2 0x02000000 0x10000>;
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interrupts = <15>;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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iofpga@3,00000000 {
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compatible = "arm,amba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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v2m_sysreg: sysreg@010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x010000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_sysctl: sysctl@020000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x020000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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};
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aaci@040000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x040000 0x1000>;
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interrupts = <11>;
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clocks = <&v2m_clk24mhz>;
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clock-names = "apb_pclk";
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};
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mmci@050000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x050000 0x1000>;
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interrupts = <9 10>;
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cd-gpios = <&v2m_sysreg 0 0>;
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wp-gpios = <&v2m_sysreg 1 0>;
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max-frequency = <12000000>;
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vmmc-supply = <&v2m_fixed_3v3>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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kmi@060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x060000 0x1000>;
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interrupts = <12>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x070000 0x1000>;
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interrupts = <13>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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v2m_serial0: uart@090000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x090000 0x1000>;
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interrupts = <5>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@0a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <6>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: uart@0b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b0000 0x1000>;
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interrupts = <7>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: uart@0c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c0000 0x1000>;
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interrupts = <8>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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wdt@0f0000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f0000 0x1000>;
|
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interrupts = <0>;
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clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
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clock-names = "wdogclk", "apb_pclk";
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};
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|
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v2m_timer01: timer@110000 {
|
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compatible = "arm,sp804", "arm,primecell";
|
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reg = <0x110000 0x1000>;
|
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interrupts = <2>;
|
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clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
|
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
|
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|
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v2m_timer23: timer@120000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x120000 0x1000>;
|
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interrupts = <3>;
|
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clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
|
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clock-names = "timclken1", "timclken2", "apb_pclk";
|
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};
|
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|
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rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
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||||
reg = <0x170000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&v2m_clk24mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
clcd@1f0000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f0000 0x1000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
mode = "XVGA";
|
||||
use_dma = <0>;
|
||||
framebuffer = <0x18000000 0x00180000>;
|
||||
};
|
||||
|
||||
virtio_block@0130000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <0x2a>;
|
||||
};
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus", "simple-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
v2m_oscclk1: osc@1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 63500000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
reset@0 {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga@0 {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown@0 {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot@0 {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode@0 {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue