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Add support to export a /cpus node to the device tree.
This patch creates and populates the /cpus node in a device tree based on the existing topology. It uses the minimum required nodes and properties to satisfy the binding as specified in https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0
This commit is contained in:
Javier Almansa Sobrino
parent
d35403feab
commit
780dd2b310
2 changed files with 172 additions and 3 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -14,15 +14,20 @@
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* that.
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*/
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#include <errno.h>
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#include <stdio.h>
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#include <string.h>
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#include <libfdt.h>
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#include <arch.h>
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#include <common/debug.h>
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#include <common/fdt_fixup.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/console.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <common/fdt_fixup.h>
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static int append_psci_compatible(void *fdt, int offs, const char *str)
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{
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@ -210,3 +215,165 @@ int fdt_add_reserved_memory(void *dtb, const char *node_name,
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return 0;
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}
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/*******************************************************************************
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* fdt_add_cpu() Add a new CPU node to the DT
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* @dtb: Pointer to the device tree blob in memory
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* @parent: Offset of the parent node
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* @mpidr: MPIDR for the current CPU
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*
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* Create and add a new cpu node to a DTB.
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*
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* Return the offset of the new node or a negative value in case of error
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******************************************************************************/
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static int fdt_add_cpu(void *dtb, int parent, u_register_t mpidr)
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{
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int cpu_offs;
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int err;
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char snode_name[15];
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uint64_t reg_prop;
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reg_prop = mpidr & MPID_MASK & ~MPIDR_MT_MASK;
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snprintf(snode_name, sizeof(snode_name), "cpu@%x",
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(unsigned int)reg_prop);
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cpu_offs = fdt_add_subnode(dtb, parent, snode_name);
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if (cpu_offs < 0) {
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ERROR ("FDT: add subnode \"%s\" failed: %i\n",
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snode_name, cpu_offs);
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return cpu_offs;
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}
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err = fdt_setprop_string(dtb, cpu_offs, "compatible", "arm,armv8");
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"compatible", cpu_offs);
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return err;
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}
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err = fdt_setprop_u64(dtb, cpu_offs, "reg", reg_prop);
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"reg", cpu_offs);
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return err;
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}
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err = fdt_setprop_string(dtb, cpu_offs, "device_type", "cpu");
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"device_type", cpu_offs);
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return err;
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}
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err = fdt_setprop_string(dtb, cpu_offs, "enable-method", "psci");
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"enable-method", cpu_offs);
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return err;
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}
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return cpu_offs;
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}
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/******************************************************************************
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* fdt_add_cpus_node() - Add the cpus node to the DTB
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* @dtb: pointer to the device tree blob in memory
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* @afflv0: Maximum number of threads per core (affinity level 0).
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* @afflv1: Maximum number of CPUs per cluster (affinity level 1).
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* @afflv2: Maximum number of clusters (affinity level 2).
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*
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* Iterate over all the possible MPIDs given the maximum affinity levels and
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* add a cpus node to the DTB with all the valid CPUs on the system.
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* If there is already a /cpus node, exit gracefully
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*
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* A system with two CPUs would generate a node equivalent or similar to:
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*
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* cpus {
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* #address-cells = <2>;
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* #size-cells = <0>;
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*
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* cpu0: cpu@0 {
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* compatible = "arm,armv8";
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* reg = <0x0 0x0>;
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* device_type = "cpu";
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* enable-method = "psci";
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* };
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* cpu1: cpu@10000 {
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* compatible = "arm,armv8";
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* reg = <0x0 0x100>;
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* device_type = "cpu";
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* enable-method = "psci";
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* };
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* };
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*
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* Full documentation about the CPU bindings can be found at:
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* https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt
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*
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* Return the offset of the node or a negative value on error.
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******************************************************************************/
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int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
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unsigned int afflv1, unsigned int afflv2)
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{
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int offs;
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int err;
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unsigned int i, j, k;
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u_register_t mpidr;
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int cpuid;
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if (fdt_path_offset(dtb, "/cpus") >= 0) {
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return -EEXIST;
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}
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offs = fdt_add_subnode(dtb, 0, "cpus");
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if (offs < 0) {
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ERROR ("FDT: add subnode \"cpus\" node to parent node failed");
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return offs;
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}
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err = fdt_setprop_u32(dtb, offs, "#address-cells", 2);
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"#address-cells", offs);
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return err;
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}
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err = fdt_setprop_u32(dtb, offs, "#size-cells", 0);
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"#size-cells", offs);
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return err;
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}
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/*
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* Populate the node with the CPUs.
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* As libfdt prepends subnodes within a node, reverse the index count
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* so the CPU nodes would be better ordered.
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*/
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for (i = afflv2; i > 0U; i--) {
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for (j = afflv1; j > 0U; j--) {
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for (k = afflv0; k > 0U; k--) {
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mpidr = ((i - 1) << MPIDR_AFF2_SHIFT) |
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((j - 1) << MPIDR_AFF1_SHIFT) |
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((k - 1) << MPIDR_AFF0_SHIFT) |
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(read_mpidr_el1() & MPIDR_MT_MASK);
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cpuid = plat_core_pos_by_mpidr(mpidr);
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if (cpuid >= 0) {
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/* Valid MPID found */
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err = fdt_add_cpu(dtb, offs, mpidr);
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if (err < 0) {
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ERROR ("FDT: %s 0x%08x\n",
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"error adding CPU",
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(uint32_t)mpidr);
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return err;
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}
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}
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}
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}
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}
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return offs;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -11,5 +11,7 @@ int dt_add_psci_node(void *fdt);
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int dt_add_psci_cpu_enable_methods(void *fdt);
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int fdt_add_reserved_memory(void *dtb, const char *node_name,
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uintptr_t base, size_t size);
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int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
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unsigned int afflv1, unsigned int afflv2);
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#endif /* FDT_FIXUP_H */
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