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Merge "fix(cpus): workaround for Cortex-A715 erratum 2344187" into integration

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Lauren Wehrmeister 2024-03-07 16:52:46 +01:00 • committed by TrustedFirmware Code Review
commit 77b30cbabf
5 changed files with 44 additions and 1 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -895,6 +895,10 @@ For Cortex-A715, the following errata build flags are defined :
Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0.
It is fixed in r1p1.
- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to
Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is
fixed in r1p1.
- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to
Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
It is fixed in r1p1.

4
include/arch/aarch64/arch.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -1401,6 +1401,8 @@
#define RGSR_EL1 S3_0_C1_C0_5
#define GCR_EL1 S3_0_C1_C0_6
#define GCR_EL1_RRND_BIT (UL(1) << 16)
/*******************************************************************************
* Armv8.5 - Random Number Generator Registers
******************************************************************************/

5
include/lib/cpus/aarch64/cortex_a715.h
View file

@ -22,6 +22,11 @@
******************************************************************************/
#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0
#define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1
#define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2
#define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/

28
lib/cpus/aarch64/cortex_a715.S
View file

@ -32,6 +32,34 @@ workaround_reset_end cortex_a715, ERRATUM(2331818)
check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0)
workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187
/* GCR_EL1 is only present with FEAT_MTE2. */
mrs x1, ID_AA64PFR1_EL1
ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
cmp x0, #MTE_IMPLEMENTED_ELX
bne #1f
sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT
1:
/* Mitigation upon ERETAA and ERETAB. */
mov x0, #2
msr CORTEX_A715_CPUPSELR_EL3, x0
isb
ldr x0, =0xd69f0bff
msr CORTEX_A715_CPUPOR_EL3, x0
ldr x0, =0xfffffbff
msr CORTEX_A715_CPUPMR_EL3, x0
mov x1, #0
orr x1, x1, #(1<<0)
orr x1, x1, #(3<<4)
orr x1, x1, #(0xf<<6)
orr x1, x1, #(1<<13)
orr x1, x1, #(1<<53)
msr CORTEX_A715_CPUPCR_EL3, x1
workaround_reset_end cortex_a715, ERRATUM(2344187)
check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0)
workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947
sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33)
workaround_reset_end cortex_a715, ERRATUM(2420947)

4
lib/cpus/cpu-ops.mk
View file

@ -920,6 +920,10 @@ CPU_FLAG_LIST += ERRATA_V2_2801372
# to revisions r0p0 and r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2331818
# Flag to apply erratum 2344187 workaround during reset. This erratum applies
# to revisions r0p0, and r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2344187
# Flag to apply erratum 2420947 workaround during reset. This erratum applies
# only to revision r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2420947