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Aarch32 xlat_tables lib: Fix MISRA-2012 defects
This patch fixes violation of Rules 2.1, 7.3, 10.1, 10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by MISRA-2012 scan and adds braces for conditional statements according to the TF-A coding style. Change-Id: Ib2463601fb43d955c3d901102b6dceaaad6614f3 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
Alexei Fedorov
parent
833abc61a4
commit
77a386907a
1 changed files with 104 additions and 89 deletions
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
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* Copyright (c) 2014-2019, Arm Limited. All rights reserved.
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* Copyright (c) 2014-2020, Arm Limited. All rights reserved.
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* Copyright (c) 2014, STMicroelectronics International N.V.
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* All rights reserved.
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*
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@ -30,8 +30,8 @@ This module is to be used when LPAE is not supported"
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CASSERT(PLAT_VIRT_ADDR_SPACE_SIZE == (1ULL << 32), invalid_vaddr_space_size);
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CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
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#define MMU32B_UNSET_DESC ~0ul
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#define MMU32B_INVALID_DESC 0ul
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#define MMU32B_UNSET_DESC ~0UL
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#define MMU32B_INVALID_DESC 0UL
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#define MT_UNKNOWN ~0U
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@ -40,38 +40,38 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
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*/
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/* Sharable */
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#define MMU32B_TTB_S (1 << 1)
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#define MMU32B_TTB_S (1U << 1)
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/* Not Outer Sharable */
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#define MMU32B_TTB_NOS (1 << 5)
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#define MMU32B_TTB_NOS (1U << 5)
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/* Normal memory, Inner Non-cacheable */
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#define MMU32B_TTB_IRGN_NC 0
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#define MMU32B_TTB_IRGN_NC 0U
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/* Normal memory, Inner Write-Back Write-Allocate Cacheable */
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#define MMU32B_TTB_IRGN_WBWA (1 << 6)
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#define MMU32B_TTB_IRGN_WBWA (1U << 6)
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/* Normal memory, Inner Write-Through Cacheable */
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#define MMU32B_TTB_IRGN_WT 1
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#define MMU32B_TTB_IRGN_WT 1U
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/* Normal memory, Inner Write-Back no Write-Allocate Cacheable */
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#define MMU32B_TTB_IRGN_WB (1 | (1 << 6))
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#define MMU32B_TTB_IRGN_WB (1U | (1U << 6))
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/* Normal memory, Outer Write-Back Write-Allocate Cacheable */
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#define MMU32B_TTB_RNG_WBWA (1 << 3)
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#define MMU32B_TTB_RNG_WBWA (1U << 3)
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#define MMU32B_DEFAULT_ATTRS \
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(MMU32B_TTB_S | MMU32B_TTB_NOS | \
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MMU32B_TTB_IRGN_WBWA | MMU32B_TTB_RNG_WBWA)
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/* armv7 memory mapping attributes: section mapping */
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#define SECTION_SECURE (0 << 19)
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#define SECTION_NOTSECURE (1 << 19)
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#define SECTION_SHARED (1 << 16)
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#define SECTION_NOTGLOBAL (1 << 17)
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#define SECTION_ACCESS_FLAG (1 << 10)
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#define SECTION_UNPRIV (1 << 11)
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#define SECTION_RO (1 << 15)
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#define SECTION_SECURE (0U << 19)
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#define SECTION_NOTSECURE (1U << 19)
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#define SECTION_SHARED (1U << 16)
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#define SECTION_NOTGLOBAL (1U << 17)
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#define SECTION_ACCESS_FLAG (1U << 10)
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#define SECTION_UNPRIV (1U << 11)
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#define SECTION_RO (1U << 15)
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#define SECTION_TEX(tex) ((((tex) >> 2) << 12) | \
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((((tex) >> 1) & 0x1) << 3) | \
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(((tex) & 0x1) << 2))
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@ -80,16 +80,16 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
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#define SECTION_NORMAL_CACHED \
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SECTION_TEX(MMU32B_ATTR_IWBWA_OWBWA_INDEX)
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#define SECTION_XN (1 << 4)
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#define SECTION_PXN (1 << 0)
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#define SECTION_SECTION (2 << 0)
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#define SECTION_XN (1U << 4)
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#define SECTION_PXN (1U << 0)
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#define SECTION_SECTION (2U << 0)
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#define SECTION_PT_NOTSECURE (1 << 3)
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#define SECTION_PT_PT (1 << 0)
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#define SECTION_PT_NOTSECURE (1U << 3)
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#define SECTION_PT_PT (1U << 0)
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#define SMALL_PAGE_SMALL_PAGE (1 << 1)
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#define SMALL_PAGE_SHARED (1 << 10)
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#define SMALL_PAGE_NOTGLOBAL (1 << 11)
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#define SMALL_PAGE_SMALL_PAGE (1U << 1)
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#define SMALL_PAGE_SHARED (1U << 10)
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#define SMALL_PAGE_NOTGLOBAL (1U << 11)
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#define SMALL_PAGE_TEX(tex) ((((tex) >> 2) << 6) | \
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((((tex) >> 1) & 0x1) << 3) | \
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(((tex) & 0x1) << 2))
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@ -99,39 +99,39 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
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SMALL_PAGE_TEX(MMU32B_ATTR_DEVICE_INDEX)
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#define SMALL_PAGE_NORMAL_CACHED \
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SMALL_PAGE_TEX(MMU32B_ATTR_IWBWA_OWBWA_INDEX)
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#define SMALL_PAGE_ACCESS_FLAG (1 << 4)
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#define SMALL_PAGE_UNPRIV (1 << 5)
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#define SMALL_PAGE_RO (1 << 9)
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#define SMALL_PAGE_XN (1 << 0)
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#define SMALL_PAGE_ACCESS_FLAG (1U << 4)
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#define SMALL_PAGE_UNPRIV (1U << 5)
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#define SMALL_PAGE_RO (1U << 9)
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#define SMALL_PAGE_XN (1U << 0)
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/* The TEX, C and B bits concatenated */
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#define MMU32B_ATTR_DEVICE_INDEX 0x0
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#define MMU32B_ATTR_IWBWA_OWBWA_INDEX 0x1
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#define MMU32B_ATTR_DEVICE_INDEX 0U
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#define MMU32B_ATTR_IWBWA_OWBWA_INDEX 1U
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#define MMU32B_PRRR_IDX(idx, tr, nos) (((tr) << (2 * (idx))) | \
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((uint32_t)(nos) << ((idx) + 24)))
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#define MMU32B_NMRR_IDX(idx, ir, or) (((ir) << (2 * (idx))) | \
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((uint32_t)(or) << (2 * (idx) + 16)))
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#define MMU32B_PRRR_DS0 (1 << 16)
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#define MMU32B_PRRR_DS1 (1 << 17)
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#define MMU32B_PRRR_NS0 (1 << 18)
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#define MMU32B_PRRR_NS1 (1 << 19)
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#define MMU32B_PRRR_DS0 (1U << 16)
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#define MMU32B_PRRR_DS1 (1U << 17)
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#define MMU32B_PRRR_NS0 (1U << 18)
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#define MMU32B_PRRR_NS1 (1U << 19)
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#define DACR_DOMAIN(num, perm) ((perm) << ((num) * 2))
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#define DACR_DOMAIN_PERM_NO_ACCESS 0x0
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#define DACR_DOMAIN_PERM_CLIENT 0x1
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#define DACR_DOMAIN_PERM_MANAGER 0x3
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#define DACR_DOMAIN_PERM_NO_ACCESS 0U
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#define DACR_DOMAIN_PERM_CLIENT 1U
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#define DACR_DOMAIN_PERM_MANAGER 3U
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#define NUM_1MB_IN_4GB (1U << 12)
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#define NUM_4K_IN_1MB (1U << 8)
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#define NUM_1MB_IN_4GB (1UL << 12)
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#define NUM_4K_IN_1MB (1UL << 8)
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#define ONE_MB_SHIFT 20
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/* mmu 32b integration */
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#define MMU32B_L1_TABLE_SIZE (NUM_1MB_IN_4GB * 4)
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#define MMU32B_L2_TABLE_SIZE (NUM_4K_IN_1MB * 4)
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#define MMU32B_L1_TABLE_ALIGN (1 << 14)
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#define MMU32B_L2_TABLE_ALIGN (1 << 10)
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#define MMU32B_L1_TABLE_ALIGN (1U << 14)
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#define MMU32B_L2_TABLE_ALIGN (1U << 10)
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static unsigned int next_xlat;
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static unsigned long long xlat_max_pa;
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@ -190,8 +190,9 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
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assert(IS_PAGE_ALIGNED(base_va));
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assert(IS_PAGE_ALIGNED(size));
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if (size == 0U)
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if (size == 0U) {
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return;
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}
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assert(base_pa < end_pa); /* Check for overflows */
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assert(base_va < end_va);
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@ -249,8 +250,9 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
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#endif /* ENABLE_ASSERTIONS */
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/* Find correct place in mmap to insert new region */
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while ((mm->base_va < base_va) && (mm->size != 0U))
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while ((mm->base_va < base_va) && (mm->size != 0U)) {
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++mm;
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}
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/*
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* If a section is contained inside another one with the same base
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@ -263,8 +265,9 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
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* This is required for mmap_region_attr() to get the attributes of the
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* small region correctly.
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*/
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while ((mm->base_va == base_va) && (mm->size > size))
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while ((mm->base_va == base_va) && (mm->size > size)) {
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++mm;
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}
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/* Make room for new region by moving other regions up by one place */
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(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
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@ -277,10 +280,12 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
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mm->size = size;
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mm->attr = attr;
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if (end_pa > xlat_max_pa)
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if (end_pa > xlat_max_pa) {
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xlat_max_pa = end_pa;
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if (end_va > xlat_max_va)
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}
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if (end_va > xlat_max_va) {
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xlat_max_va = end_va;
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}
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}
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/* map all memory as shared/global/domain0/no-usr access */
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@ -290,42 +295,44 @@ static uint32_t mmap_desc(unsigned attr, unsigned int addr_pa,
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uint32_t desc;
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switch (level) {
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case 1:
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assert(!(addr_pa & (MMU32B_L1_TABLE_ALIGN - 1)));
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case 1U:
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assert((addr_pa & (MMU32B_L1_TABLE_ALIGN - 1)) == 0U);
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desc = SECTION_SECTION | SECTION_SHARED;
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desc |= attr & MT_NS ? SECTION_NOTSECURE : 0;
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desc |= (attr & MT_NS) != 0U ? SECTION_NOTSECURE : 0U;
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desc |= SECTION_ACCESS_FLAG;
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desc |= attr & MT_RW ? 0 : SECTION_RO;
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desc |= (attr & MT_RW) != 0U ? 0U : SECTION_RO;
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desc |= attr & MT_MEMORY ?
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desc |= (attr & MT_MEMORY) != 0U ?
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SECTION_NORMAL_CACHED : SECTION_DEVICE;
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if ((attr & MT_RW) || !(attr & MT_MEMORY))
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if (((attr & MT_RW) != 0U) || ((attr & MT_MEMORY) == 0U)) {
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desc |= SECTION_XN;
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}
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break;
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case 2:
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assert(!(addr_pa & (MMU32B_L2_TABLE_ALIGN - 1)));
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case 2U:
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assert((addr_pa & (MMU32B_L2_TABLE_ALIGN - 1)) == 0U);
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desc = SMALL_PAGE_SMALL_PAGE | SMALL_PAGE_SHARED;
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desc |= SMALL_PAGE_ACCESS_FLAG;
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desc |= attr & MT_RW ? 0 : SMALL_PAGE_RO;
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desc |= (attr & MT_RW) != 0U ? 0U : SMALL_PAGE_RO;
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desc |= attr & MT_MEMORY ?
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desc |= (attr & MT_MEMORY) != 0U ?
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SMALL_PAGE_NORMAL_CACHED : SMALL_PAGE_DEVICE;
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if ((attr & MT_RW) || !(attr & MT_MEMORY))
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if (((attr & MT_RW) != 0U) || ((attr & MT_MEMORY) == 0U)) {
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desc |= SMALL_PAGE_XN;
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}
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break;
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default:
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panic();
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}
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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/* dump only the non-lpae level 2 tables */
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if (level == 2) {
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if (level == 2U) {
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printf(attr & MT_MEMORY ? "MEM" : "dev");
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printf(attr & MT_RW ? "-rw" : "-RO");
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printf(attr & MT_NS ? "-NS" : "-S");
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@ -357,26 +364,31 @@ static unsigned int mmap_region_attr(const mmap_region_t *mm, uintptr_t base_va,
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*/
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for ( ; ; ++mm) {
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if (mm->size == 0U)
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if (mm->size == 0U) {
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return ret; /* Reached end of list */
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}
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if (mm->base_va > (base_va + size - 1U))
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if (mm->base_va > (base_va + size - 1U)) {
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return ret; /* Next region is after area so end */
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}
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if ((mm->base_va + mm->size - 1U) < base_va)
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if ((mm->base_va + mm->size - 1U) < base_va) {
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continue; /* Next region has already been overtaken */
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}
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if ((ret == 0U) && (mm->attr == *attr))
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if ((ret == 0U) && (mm->attr == *attr)) {
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continue; /* Region doesn't override attribs so skip */
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}
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if ((mm->base_va > base_va) ||
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((mm->base_va + mm->size - 1U) < (base_va + size - 1U)))
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((mm->base_va + mm->size - 1U) <
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(base_va + size - 1U))) {
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return MT_UNKNOWN; /* Region doesn't fully cover area */
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}
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*attr = mm->attr;
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ret = 0U;
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}
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return ret;
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}
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static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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@ -384,16 +396,16 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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uint32_t *table,
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unsigned int level)
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{
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unsigned int level_size_shift = (level == 1) ?
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unsigned int level_size_shift = (level == 1U) ?
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ONE_MB_SHIFT : FOUR_KB_SHIFT;
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unsigned int level_size = 1 << level_size_shift;
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unsigned int level_index_mask = (level == 1) ?
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unsigned int level_size = 1U << level_size_shift;
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unsigned int level_index_mask = (level == 1U) ?
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(NUM_1MB_IN_4GB - 1) << ONE_MB_SHIFT :
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(NUM_4K_IN_1MB - 1) << FOUR_KB_SHIFT;
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assert(level == 1 || level == 2);
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assert((level == 1U) || (level == 2U));
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VERBOSE("init xlat table at %p (level%1d)\n", (void *)table, level);
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VERBOSE("init xlat table at %p (level%1u)\n", (void *)table, level);
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do {
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uint32_t desc = MMU32B_UNSET_DESC;
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@ -405,15 +417,17 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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}
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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/* dump only non-lpae level 2 tables content */
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if (level == 2)
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if (level == 2U) {
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printf(" 0x%lx %x " + 6 - 2 * level,
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base_va, level_size);
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}
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#endif
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if (mm->base_va >= base_va + level_size) {
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/* Next region is after area so nothing to map yet */
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desc = MMU32B_INVALID_DESC;
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} else if (mm->base_va <= base_va && mm->base_va + mm->size >=
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base_va + level_size) {
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} else if ((mm->base_va <= base_va) &&
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(mm->base_va + mm->size) >=
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(base_va + level_size)) {
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/* Next region covers all of area */
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unsigned int attr = mm->attr;
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unsigned int r = mmap_region_attr(mm, base_va,
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@ -436,8 +450,8 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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*/
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if (*table) {
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assert((*table & 3) == SECTION_PT_PT);
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assert(!(*table & SECTION_PT_NOTSECURE) ==
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!(mm->attr & MT_NS));
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assert(((*table & SECTION_PT_NOTSECURE) == 0U)
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== ((mm->attr & MT_NS) == 0U));
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xlat_table = (*table) &
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~(MMU32B_L1_TABLE_ALIGN - 1);
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@ -447,11 +461,11 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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next_xlat * MMU32B_L2_TABLE_SIZE;
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next_xlat++;
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assert(next_xlat <= MAX_XLAT_TABLES);
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memset((char *)xlat_table, 0,
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(void)memset((char *)xlat_table, 0,
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MMU32B_L2_TABLE_SIZE);
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desc = xlat_table | SECTION_PT_PT;
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desc |= mm->attr & MT_NS ?
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desc |= (mm->attr & MT_NS) != 0U ?
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SECTION_PT_NOTSECURE : 0;
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}
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/* Recurse to fill in new table */
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@ -461,12 +475,13 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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}
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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/* dump only non-lpae level 2 tables content */
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if (level == 2)
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if (level == 2U) {
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printf("\n");
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}
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#endif
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*table++ = desc;
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base_va += level_size;
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} while (mm->size && (base_va & level_index_mask));
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} while ((mm->size != 0U) && ((base_va & level_index_mask) != 0U));
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return mm;
|
||||
}
|
||||
|
|
@ -475,17 +490,16 @@ void init_xlat_tables(void)
|
|||
{
|
||||
print_mmap();
|
||||
|
||||
assert(!((unsigned int)mmu_l1_base & (MMU32B_L1_TABLE_ALIGN - 1)));
|
||||
assert(!((unsigned int)mmu_l2_base & (MMU32B_L2_TABLE_ALIGN - 1)));
|
||||
assert(((unsigned int)mmu_l1_base & (MMU32B_L1_TABLE_ALIGN - 1)) == 0U);
|
||||
assert(((unsigned int)mmu_l2_base & (MMU32B_L2_TABLE_ALIGN - 1)) == 0U);
|
||||
|
||||
memset(mmu_l1_base, 0, MMU32B_L1_TABLE_SIZE);
|
||||
(void)memset(mmu_l1_base, 0, MMU32B_L1_TABLE_SIZE);
|
||||
|
||||
init_xlation_table_inner(mmap, 0, (uint32_t *)mmu_l1_base, 1);
|
||||
|
||||
VERBOSE("init xlat - max_va=%p, max_pa=%llx\n",
|
||||
(void *)xlat_max_va, xlat_max_pa);
|
||||
assert(xlat_max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
|
||||
assert(xlat_max_pa <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
|
||||
assert(xlat_max_pa <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -499,7 +513,7 @@ void enable_mmu_svc_mon(unsigned int flags)
|
|||
unsigned int sctlr;
|
||||
|
||||
assert(IS_IN_SECURE());
|
||||
assert((read_sctlr() & SCTLR_M_BIT) == 0);
|
||||
assert((read_sctlr() & SCTLR_M_BIT) == 0U);
|
||||
|
||||
/* Enable Access flag (simplified access permissions) and TEX remap */
|
||||
write_sctlr(read_sctlr() | SCTLR_AFE_BIT | SCTLR_TRE_BIT);
|
||||
|
|
@ -522,7 +536,7 @@ void enable_mmu_svc_mon(unsigned int flags)
|
|||
|
||||
/* set MMU base xlat table entry (use only TTBR0) */
|
||||
write_ttbr0((uint32_t)mmu_l1_base | MMU32B_DEFAULT_ATTRS);
|
||||
write_ttbr1(0);
|
||||
write_ttbr1(0U);
|
||||
|
||||
/*
|
||||
* Ensure all translation table writes have drained
|
||||
|
|
@ -535,14 +549,15 @@ void enable_mmu_svc_mon(unsigned int flags)
|
|||
|
||||
sctlr = read_sctlr();
|
||||
sctlr |= SCTLR_M_BIT;
|
||||
#if ARMV7_SUPPORTS_VIRTUALIZATION
|
||||
#ifdef ARMV7_SUPPORTS_VIRTUALIZATION
|
||||
sctlr |= SCTLR_WXN_BIT;
|
||||
#endif
|
||||
|
||||
if (flags & DISABLE_DCACHE)
|
||||
if ((flags & DISABLE_DCACHE) != 0U) {
|
||||
sctlr &= ~SCTLR_C_BIT;
|
||||
else
|
||||
} else {
|
||||
sctlr |= SCTLR_C_BIT;
|
||||
}
|
||||
|
||||
write_sctlr(sctlr);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue