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perf(cpus): inline cpu_rev_var checks
We strive to apply errata as close to reset as possible with as few
things enabled as possible. Importantly, the I-cache will not be
enabled. This means that repeated branches to these tiny functions must
be re-fetched all the way from memory each time which has glacial speed.
Cores are allowed to fetch things ahead of time though as long as
execution is fairly linear. So we can trade a little bit of space (3 to
7 instructions per erratum) to keep things linear and not have to go to
memory.
While we're at it, optimise the the cpu_rev_var_{ls, hs, range}
functions to take up less space. Dropping the moves allows for a bit of
assembly magic that produces the same result in 2 and 3 instructions
respectively.
Change-Id: I51608352f23b2244ea7a99e76c10892d257f12bf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
Boyan Karatotev
parent
b62673c645
commit
7791ce21a6
5 changed files with 48 additions and 76 deletions
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@ -479,8 +479,35 @@
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.endm
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/*
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* Helpers to select which revisions errata apply to. Don't leave a link
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* register as the cpu_rev_var_*** will call the ret and we can save on one.
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* Helpers to report if an erratum applies. Compares the given revision variant
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* to the given value. Return ERRATA_APPLIES or ERRATA_NOT_APPLIES accordingly.
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*
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* _rev_num: the given revision variant. Or
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* _rev_num_lo,_rev_num_hi: the lower and upper bounds of the revision variant
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*
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* in body:
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* clobber: x0
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* argument: x0 - cpu_rev_var
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*/
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.macro cpu_rev_var_ls _rev_num:req
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cmp x0, #\_rev_num
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cset x0, ls
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.endm
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.macro cpu_rev_var_hs _rev_num:req
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cmp x0, #\_rev_num
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cset x0, hs
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.endm
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.macro cpu_rev_var_range _rev_num_lo:req, _rev_num_hi:req
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cmp x0, #\_rev_num_lo
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mov x1, #\_rev_num_hi
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ccmp x0, x1, #2, hs
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cset x0, ls
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.endm
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/*
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* Helpers to select which revisions errata apply to.
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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@ -496,28 +523,27 @@
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* Revision to apply to
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*
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* in body:
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* clobber: x0 to x4
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* clobber: x0 to x1
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* argument: x0 - cpu_rev_var
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*/
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.macro check_erratum_ls _cpu:req, _cve:req, _id:req, _rev_num:req
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func check_erratum_\_cpu\()_\_id
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mov x1, #\_rev_num
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b cpu_rev_var_ls
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cpu_rev_var_ls \_rev_num
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ret
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endfunc check_erratum_\_cpu\()_\_id
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.endm
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.macro check_erratum_hs _cpu:req, _cve:req, _id:req, _rev_num:req
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func check_erratum_\_cpu\()_\_id
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mov x1, #\_rev_num
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b cpu_rev_var_hs
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cpu_rev_var_hs \_rev_num
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ret
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endfunc check_erratum_\_cpu\()_\_id
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.endm
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.macro check_erratum_range _cpu:req, _cve:req, _id:req, _rev_num_lo:req, _rev_num_hi:req
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func check_erratum_\_cpu\()_\_id
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mov x1, #\_rev_num_lo
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mov x2, #\_rev_num_hi
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b cpu_rev_var_range
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cpu_rev_var_range \_rev_num_lo, \_rev_num_hi
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ret
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endfunc check_erratum_\_cpu\()_\_id
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.endm
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@ -532,7 +558,10 @@
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endfunc check_erratum_\_cpu\()_\_id
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.endm
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/* provide a shorthand for the name format for annoying errata */
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/*
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* provide a shorthand for the name format for annoying errata
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* body: clobber x0 to x3
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*/
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.macro check_erratum_custom_start _cpu:req, _cve:req, _id:req
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func check_erratum_\_cpu\()_\_id
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.endm
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@ -51,8 +51,7 @@ workaround_reset_end cortex_a55, ERRATUM(778703)
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check_erratum_custom_start cortex_a55, ERRATUM(778703)
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mov x16, x30
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mov x1, #0x00
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bl cpu_rev_var_ls
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cpu_rev_var_ls CPU_REV(0, 0)
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/*
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* Check that no private L2 cache is configured
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*/
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@ -345,11 +345,10 @@ check_erratum_ls cortex_a76, ERRATUM(1275112), CPU_REV(3, 0)
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check_erratum_custom_start cortex_a76, ERRATUM(1286807)
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#if ERRATA_A76_1286807
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mov x0, #ERRATA_APPLIES
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ret
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#else
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mov x1, #0x30
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b cpu_rev_var_ls
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cpu_rev_var_ls CPU_REV(3, 0)
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#endif
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ret
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check_erratum_custom_end cortex_a76, ERRATUM(1286807)
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workaround_reset_start cortex_a76, ERRATUM(1791580), ERRATA_A76_1791580
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@ -420,11 +419,10 @@ endfunc cortex_a76_disable_wa_cve_2018_3639
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check_erratum_custom_start cortex_a76, ERRATUM(1165522)
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#if ERRATA_A76_1165522
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mov x0, #ERRATA_APPLIES
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ret
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#else
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mov x1, #0x30
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b cpu_rev_var_ls
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cpu_rev_var_ls CPU_REV(3, 0)
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#endif
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ret
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check_erratum_custom_end cortex_a76, ERRATUM(1165522)
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check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -36,8 +36,7 @@ check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
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/* move cpu revision in again and compare against r0p0 */
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mov x0, x7
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mov x1, #CPU_REV(0, 0)
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bl cpu_rev_var_ls
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cpu_rev_var_ls CPU_REV(0, 0)
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cbz x0, 1f
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ldr x0, =0x0
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -236,59 +236,6 @@ func cpu_get_rev_var
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ret
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endfunc cpu_get_rev_var
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/*
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* Compare the CPU's revision-variant (x0) with a given value (x1), for errata
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* application purposes. If the revision-variant is less than or same as a given
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* value, indicates that errata applies; otherwise not.
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*
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* Shall clobber: x0-x3
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*/
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.globl cpu_rev_var_ls
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func cpu_rev_var_ls
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mov x2, #ERRATA_APPLIES
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mov x3, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x0, x2, x3, ls
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ret
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endfunc cpu_rev_var_ls
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/*
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* Compare the CPU's revision-variant (x0) with a given value (x1), for errata
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* application purposes. If the revision-variant is higher than or same as a
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* given value, indicates that errata applies; otherwise not.
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*
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* Shall clobber: x0-x3
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*/
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.globl cpu_rev_var_hs
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func cpu_rev_var_hs
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mov x2, #ERRATA_APPLIES
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mov x3, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x0, x2, x3, hs
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ret
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endfunc cpu_rev_var_hs
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/*
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* Compare the CPU's revision-variant (x0) with a given range (x1 - x2), for errata
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* application purposes. If the revision-variant is between or includes the given
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* values, this indicates that errata applies; otherwise not.
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*
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* Shall clobber: x0-x4
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*/
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.globl cpu_rev_var_range
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func cpu_rev_var_range
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mov x3, #ERRATA_APPLIES
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mov x4, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x1, x3, x4, hs
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cbz x1, 1f
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cmp x0, x2
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csel x1, x3, x4, ls
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1:
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mov x0, x1
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ret
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endfunc cpu_rev_var_range
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/*
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* int check_wa_cve_2017_5715(void);
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*
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