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feat(zynqmp): remove pm_ioctl_set_sgmii_mode api

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There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.

Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
This commit is contained in:
Ronak Jain 2023-11-02 23:05:42 -07:00
parent 93823fb6ec
commit 7414aaa1a1
5 changed files with 0 additions and 88 deletions
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1
plat/xilinx/common/include/pm_defs.h
View file

@ -68,7 +68,6 @@ enum {
IOCTL_RPU_BOOT_ADDR_CONFIG = 2, IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
IOCTL_TCM_COMB_CONFIG = 3, IOCTL_TCM_COMB_CONFIG = 3,
IOCTL_SET_TAPDELAY_BYPASS = 4, IOCTL_SET_TAPDELAY_BYPASS = 4,
IOCTL_SET_SGMII_MODE = 5,
IOCTL_SD_DLL_RESET = 6, IOCTL_SD_DLL_RESET = 6,
IOCTL_SET_SD_TAPDELAY = 7, IOCTL_SET_SD_TAPDELAY = 7,
/* Ioctl for clock driver */ /* Ioctl for clock driver */

14
plat/xilinx/zynqmp/include/zynqmp_def.h
View file

@ -221,20 +221,6 @@
#define IOU_TAPDLY_BYPASS U(0XFF180390) #define IOU_TAPDLY_BYPASS U(0XFF180390)
#define TAP_DELAY_MASK U(0x7) #define TAP_DELAY_MASK U(0x7)
/* SGMII mode */
#define IOU_GEM_CTRL U(0xFF180360)
#define IOU_GEM_CLK_CTRL U(0xFF180308)
#define SGMII_SD_MASK U(0x3)
#define SGMII_SD_OFFSET U(2)
#define SGMII_PCS_SD_0 U(0x0)
#define SGMII_PCS_SD_1 U(0x1)
#define SGMII_PCS_SD_PHY U(0x2)
#define GEM_SGMII_MASK U(0x4)
#define GEM_CLK_CTRL_MASK U(0xF)
#define GEM_CLK_CTRL_OFFSET U(5)
#define GEM_RX_SRC_SEL_GTR U(0x1)
#define GEM_SGMII_MODE U(0x4)
/* SD DLL reset */ /* SD DLL reset */
#define ZYNQMP_SD_DLL_CTRL U(0xFF180358) #define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)

65
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
View file

@ -173,67 +173,6 @@ static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(uint32_t type,
return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type); return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type);
} }
/**
* pm_ioctl_set_sgmii_mode() - Set SGMII mode for the GEM device.
* @nid: Node ID of the device.
* @value: Enable/Disable.
*
* This function enable/disable SGMII mode for the GEM device.
* While enabling SGMII mode, it also ties the GEM PCS Signal
* Detect to 1 and selects EMIO for RX clock generation.
*
* Return: Returns status, either success or error+reason.
*
*/
static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid,
uint32_t value)
{
uint32_t val, mask, shift;
enum pm_ret_status ret;
if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE) {
return PM_RET_ERROR_ARGS;
}
switch (nid) {
case NODE_ETH_0:
shift = 0;
break;
case NODE_ETH_1:
shift = 1;
break;
case NODE_ETH_2:
shift = 2;
break;
case NODE_ETH_3:
shift = 3;
break;
default:
return PM_RET_ERROR_ARGS;
}
if (value == PM_SGMII_DISABLE) {
mask = GEM_SGMII_MASK << GEM_CLK_CTRL_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0U);
} else {
/* Tie the GEM PCS Signal Detect to 1 */
mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
val = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CTRL, mask, val);
if (ret != PM_RET_SUCCESS) {
return ret;
}
/* Set the GEM to SGMII mode */
mask = GEM_CLK_CTRL_MASK << GEM_CLK_CTRL_OFFSET * shift;
val = GEM_RX_SRC_SEL_GTR | GEM_SGMII_MODE;
val <<= GEM_CLK_CTRL_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, val);
}
return ret;
}
/** /**
* pm_ioctl_sd_dll_reset() - Reset DLL logic. * pm_ioctl_sd_dll_reset() - Reset DLL logic.
* @nid: Node ID of the device. * @nid: Node ID of the device.
@ -684,9 +623,6 @@ enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
case IOCTL_SET_TAPDELAY_BYPASS: case IOCTL_SET_TAPDELAY_BYPASS:
ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2); ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2);
break; break;
case IOCTL_SET_SGMII_MODE:
ret = pm_ioctl_set_sgmii_mode(nid, arg1);
break;
case IOCTL_SD_DLL_RESET: case IOCTL_SD_DLL_RESET:
ret = pm_ioctl_sd_dll_reset(nid, arg1); ret = pm_ioctl_sd_dll_reset(nid, arg1);
break; break;
@ -752,7 +688,6 @@ enum pm_ret_status tfa_ioctl_bitmask(uint32_t *bit_mask)
IOCTL_RPU_BOOT_ADDR_CONFIG, IOCTL_RPU_BOOT_ADDR_CONFIG,
IOCTL_TCM_COMB_CONFIG, IOCTL_TCM_COMB_CONFIG,
IOCTL_SET_TAPDELAY_BYPASS, IOCTL_SET_TAPDELAY_BYPASS,
IOCTL_SET_SGMII_MODE,
IOCTL_SD_DLL_RESET, IOCTL_SD_DLL_RESET,
IOCTL_SET_SD_TAPDELAY, IOCTL_SET_SD_TAPDELAY,
IOCTL_SET_PLL_FRAC_MODE, IOCTL_SET_PLL_FRAC_MODE,

4
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
View file

@ -36,10 +36,6 @@
#define PM_TAPDELAY_BYPASS_DISABLE 0U #define PM_TAPDELAY_BYPASS_DISABLE 0U
#define PM_TAPDELAY_BYPASS_ENABLE 1U #define PM_TAPDELAY_BYPASS_ENABLE 1U
//sgmii mode
#define PM_SGMII_DISABLE 0U
#define PM_SGMII_ENABLE 1U
enum tap_delay_type { enum tap_delay_type {
PM_TAPDELAY_INPUT, PM_TAPDELAY_INPUT,
PM_TAPDELAY_OUTPUT, PM_TAPDELAY_OUTPUT,

4
plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
View file

@ -162,10 +162,6 @@ static const eemi_api_dependency api_dep_table[] = {
.id = IOCTL_SET_TAPDELAY_BYPASS, .id = IOCTL_SET_TAPDELAY_BYPASS,
.api_id = PM_MMIO_WRITE, .api_id = PM_MMIO_WRITE,
}, },
{
.id = IOCTL_SET_SGMII_MODE,
.api_id = PM_MMIO_WRITE,
},
{ {
.id = IOCTL_SD_DLL_RESET, .id = IOCTL_SD_DLL_RESET,
.api_id = PM_MMIO_WRITE, .api_id = PM_MMIO_WRITE,