From 73d98e37593f4a4044dd28f52127cdc890911c0c Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Mon, 2 Dec 2024 09:36:10 +0000 Subject: [PATCH] fix(trbe): add a tsb before context switching Just like for SPE, we need to synchronize TRBE samples before we change the context to ensure everything goes where it was intended to. If that is not done, the in-flight entries might use any piece of now incorrect context as there are no implicit ordering requirements. Prior to root context, the buffer drain hooks would have done that. But now that must happen much earlier. So add a tsb to prepare_el3_entry as well. Annoyingly, the barrier can be reordered relative to other instructions by default (rule RCKVWP). So add an isb after the psb/tsb to assure that they are ordered, at least as far as context is concerned. Then, drop the buffer draining hooks. Everything they need to do is already done by now. There's a notable difference in that there are no dsb-s now. Since EL3 does not access the buffers or the feature specific context, we don't need to wait for them to finish. Finally, drop a stray isb in the context saving macro. It is now absorbed into root context, but was missed. Change-Id: I30797a40ac7f91d0bb71ad271a1597e85092ccd5 Signed-off-by: Boyan Karatotev --- include/arch/aarch64/asm_macros.S | 4 ++++ lib/el3_runtime/aarch64/context.S | 5 ++++- lib/extensions/spe/spe.c | 1 - lib/extensions/trbe/trbe.c | 28 ---------------------------- 4 files changed, 8 insertions(+), 30 deletions(-) diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 00e482b57..197ea0600 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -262,6 +262,10 @@ hint #17 /* use the hint synonym for compatibility */ .endm + .macro tsb_csync + hint #18 /* use the hint synonym for compatibility */ + .endm + /* * Macro for using speculation barrier instruction introduced by * FEAT_SB, if it's enabled. diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index a37c7f49c..fed24f0f5 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -400,7 +400,6 @@ no_mpam: /* PMUv3 is presumed to be always present */ mrs x9, pmcr_el0 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] - isb #if CTX_INCLUDE_PAUTH_REGS /* ---------------------------------------------------------- * Save the ARMv8.3-PAuth keys as they are not banked @@ -448,6 +447,10 @@ func prepare_el3_entry #if ENABLE_SPE_FOR_NS psb_csync #endif +#if ENABLE_TRBE_FOR_NS + tsb_csync +#endif + isb save_gp_pmcr_pauth_regs setup_el3_execution_context ret diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c index 12eae355a..a8d42ab77 100644 --- a/lib/extensions/spe/spe.c +++ b/lib/extensions/spe/spe.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c index 8c1c42180..8775e40cc 100644 --- a/lib/extensions/trbe/trbe.c +++ b/lib/extensions/trbe/trbe.c @@ -7,18 +7,8 @@ #include #include #include -#include #include -static void tsb_csync(void) -{ - /* - * The assembler does not yet understand the tsb csync mnemonic - * so use the equivalent hint instruction. - */ - __asm__ volatile("hint #18"); -} - void trbe_enable(cpu_context_t *ctx) { el3_state_t *state = get_el3state_ctx(ctx); @@ -68,21 +58,3 @@ void trbe_init_el2_unused(void) */ write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); } - -static void *trbe_drain_trace_buffers_hook(const void *arg __unused) -{ - if (is_feat_trbe_supported()) { - /* - * Before switching from normal world to secure world - * the trace buffers need to be drained out to memory. This is - * required to avoid an invalid memory access when TTBR is switched - * for entry to S-EL1. - */ - tsb_csync(); - dsbnsh(); - } - - return (void *)0; -} - -SUBSCRIBE_TO_EVENT(cm_entering_secure_world, trbe_drain_trace_buffers_hook);