diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index 00e482b57..197ea0600 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -262,6 +262,10 @@
 	hint #17 /* use the hint synonym for compatibility */
 	.endm
 
+	.macro tsb_csync
+	hint #18 /* use the hint synonym for compatibility */
+	.endm
+
 	/*
 	 * Macro for using speculation barrier instruction introduced by
 	 * FEAT_SB, if it's enabled.
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index a37c7f49c..fed24f0f5 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -400,7 +400,6 @@ no_mpam:
 	/* PMUv3 is presumed to be always present */
 	mrs	x9, pmcr_el0
 	str	x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
-	isb
 #if CTX_INCLUDE_PAUTH_REGS
 	/* ----------------------------------------------------------
  	 * Save the ARMv8.3-PAuth keys as they are not banked
@@ -448,6 +447,10 @@ func prepare_el3_entry
 #if ENABLE_SPE_FOR_NS
 	psb_csync
 #endif
+#if ENABLE_TRBE_FOR_NS
+	tsb_csync
+#endif
+	isb
 	save_gp_pmcr_pauth_regs
 	setup_el3_execution_context
 	ret
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index 12eae355a..a8d42ab77 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -9,7 +9,6 @@
 #include <arch.h>
 #include <arch_features.h>
 #include <arch_helpers.h>
-#include <lib/el3_runtime/pubsub.h>
 #include <lib/extensions/spe.h>
 
 #include <plat/common/platform.h>
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c
index 8c1c42180..8775e40cc 100644
--- a/lib/extensions/trbe/trbe.c
+++ b/lib/extensions/trbe/trbe.c
@@ -7,18 +7,8 @@
 #include <arch.h>
 #include <arch_features.h>
 #include <arch_helpers.h>
-#include <lib/el3_runtime/pubsub.h>
 #include <lib/extensions/trbe.h>
 
-static void tsb_csync(void)
-{
-	/*
-	 * The assembler does not yet understand the tsb csync mnemonic
-	 * so use the equivalent hint instruction.
-	 */
-	__asm__ volatile("hint #18");
-}
-
 void trbe_enable(cpu_context_t *ctx)
 {
 	el3_state_t *state = get_el3state_ctx(ctx);
@@ -68,21 +58,3 @@ void trbe_init_el2_unused(void)
 	 */
 	write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
 }
-
-static void *trbe_drain_trace_buffers_hook(const void *arg __unused)
-{
-	if (is_feat_trbe_supported()) {
-		/*
-		 * Before switching from normal world to secure world
-		 * the trace buffers need to be drained out to memory. This is
-		 * required to avoid an invalid memory access when TTBR is switched
-		 * for entry to S-EL1.
-		 */
-		tsb_csync();
-		dsbnsh();
-	}
-
-	return (void *)0;
-}
-
-SUBSCRIBE_TO_EVENT(cm_entering_secure_world, trbe_drain_trace_buffers_hook);