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fix(cpus): workaround for Cortex-A720 erratum 2940794

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Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of the CPUACTLR2_EL1 to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I1488802e0ec7c16349c9633bb45de4d0e1faa9ad
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>
This commit is contained in:
Bipin Ravi 2024-03-12 10:29:16 -05:00
parent 57ab6d8976
commit 7385213e60
4 changed files with 22 additions and 2 deletions
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5
docs/design/cpu-specific-build-macros.rst
View file

@ -911,6 +911,11 @@ For Cortex-A715, the following errata build flags are defined :
Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
It is fixed in r1p1.
For Cortex-A720, the following errata build flags are defined :
- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to
Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
It is fixed in r0p2.
DSU Errata Workarounds
----------------------

7
include/lib/cpus/aarch64/cortex_a720.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,11 @@
/* Cortex A720 loop count for CVE-2022-23960 mitigation */
#define CORTEX_A720_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/

8
lib/cpus/aarch64/cortex_a720.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -26,6 +26,12 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794
sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37)
workaround_reset_end cortex_a720, ERRATUM(2940794)
check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1)
workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*

4
lib/cpus/cpu-ops.mk
View file

@ -936,6 +936,10 @@ CPU_FLAG_LIST += ERRATA_A715_2429384
# only to revision r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2561034
# Flag to apply erratum 2940794 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A720_2940794
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_798953