From 20ef588e86ad8f3cf13382c164463046db261feb Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Mon, 15 Nov 2021 18:07:47 +0800 Subject: [PATCH 1/2] feat(plat/mediatek/mt8195): dump EMI MPU configurations Add dump_emi_mpu_regions() to dump EMI MPU configurations. BUG=b:204347737 TEST=build pass Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f Signed-off-by: Tinghan Shen --- .../mediatek/mt8195/drivers/emi_mpu/emi_mpu.c | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c index 4330b77d5..2bb73cb1b 100644 --- a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c +++ b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c @@ -91,7 +91,26 @@ int emi_mpu_set_protection(struct emi_region_info_t *region_info) return 0; } +void dump_emi_mpu_regions(void) +{ + unsigned long apc[EMI_MPU_DGROUP_NUM], sa, ea; + + int region, i; + + /* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */ + for (region = 0; region < 8; ++region) { + for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i) + apc[i] = mmio_read_32(EMI_MPU_APC(region, i)); + sa = mmio_read_32(EMI_MPU_SA(region)); + ea = mmio_read_32(EMI_MPU_EA(region)); + + INFO("region %d:\n", region); + INFO("\tsa:0x%lx, ea:0x%lx, apc0: 0x%lx apc1: 0x%lx\n", + sa, ea, apc[0], apc[1]); + } +} + void emi_mpu_init(void) { - /* TODO: more setting for EMI MPU. */ + dump_emi_mpu_regions(); } From 690cb1265ea84851bd6405a0a6a57d2f1c9f03a3 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Mon, 15 Nov 2021 18:08:10 +0800 Subject: [PATCH 2/2] feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP 1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000. 2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF. BUG=b:204347737 TEST=build pass Signed-off-by: Tinghan Shen Signed-off-by: Trevor Wu Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc --- .../mediatek/mt8195/drivers/emi_mpu/emi_mpu.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c index 2bb73cb1b..794e21ef8 100644 --- a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c +++ b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c @@ -112,5 +112,40 @@ void dump_emi_mpu_regions(void) void emi_mpu_init(void) { + struct emi_region_info_t region_info; + + /* SCP DRAM */ + region_info.start = 0x50000000ULL; + region_info.end = 0x51400000ULL; + region_info.region = 2; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION); + emi_mpu_set_protection(®ion_info); + + /* DSP protect address */ + region_info.start = 0x60000000ULL; /* dram base addr */ + region_info.end = 0x610FFFFFULL; + region_info.region = 3; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION); + emi_mpu_set_protection(®ion_info); + + /* Forbidden All */ + region_info.start = 0x40000000ULL; /* dram base addr */ + region_info.end = 0x1FFFF0000ULL; + region_info.region = 4; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION); + emi_mpu_set_protection(®ion_info); + dump_emi_mpu_regions(); }