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feat(stm32mp15): manage OP-TEE shared memory

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On STM32MP15, there is currently an OP-TEE shared memory area at the end
of the DDR. But this area will in term be removed. To allow a smooth
transition, a new flag is added (STM32MP15_OPTEE_RSV_SHM). It reflects
the OP-TEE flag: CFG_CORE_RESERVED_SHM. The flag is enabled by default
(no behavior change). It will be set to 0 when OP-TEE is aligned, and
then later be removed.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I91146cd8a26a24be22143c212362294c1e880264
This commit is contained in:
Yann Gautier 2022-06-30 11:33:27 +02:00
parent 57ab749758
commit 722ca35ecc
4 changed files with 21 additions and 4 deletions
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9
fdts/stm32mp15-fw-config.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
*/
#include <common/tbbr/tbbr_img_def.h>
@ -14,7 +14,7 @@
#define DDR_NS_BASE STM32MP_DDR_BASE
#ifdef AARCH32_SP_OPTEE
/* OP-TEE reserved shared memory: located at DDR top */
/* OP-TEE reserved shared memory: located at DDR top or null size */
#define DDR_SHARE_SIZE STM32MP_DDR_SHMEM_SIZE
#define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE))
/* OP-TEE secure memory: located right below OP-TEE reserved shared memory */
@ -70,8 +70,11 @@
memory-ranges = <
DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR
DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0
#if STM32MP15_OPTEE_RSV_SHM
DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)>;
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)
#endif
>;
#else
memory-ranges = <
DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>;

4
plat/st/stm32mp1/platform.mk
View file

@ -65,6 +65,10 @@ STM32MP_DDR_32BIT_INTERFACE:= 1
# STM32 image header version v1.0
STM32_HEADER_VERSION_MAJOR:= 1
STM32_HEADER_VERSION_MINOR:= 0
# Add OP-TEE reserved shared memory area in mapping
STM32MP15_OPTEE_RSV_SHM := 1
$(eval $(call add_defines,STM32MP15_OPTEE_RSV_SHM))
endif
# STM32 image header binary type for BL2

5
plat/st/stm32mp1/stm32mp1_fip_def.h
View file

@ -7,8 +7,13 @@
#ifndef STM32MP1_FIP_DEF_H
#define STM32MP1_FIP_DEF_H
#if STM32MP15_OPTEE_RSV_SHM
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
#else
#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */
#endif
#if STM32MP13
#define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */

7
plat/st/stm32mp1/stm32mp1_stm32image_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
* Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -8,9 +8,14 @@
#define STM32MP1_STM32IMAGE_DEF_H
#ifdef AARCH32_SP_OPTEE
#if STM32MP15_OPTEE_RSV_SHM
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
#else
#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */
#endif
#else
#define STM32MP_DDR_S_SIZE U(0)
#define STM32MP_DDR_SHMEM_SIZE U(0)
#endif