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https://github.com/ARM-software/arm-trusted-firmware.git
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plat/marvell/armada: allow builds without MSS support
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
This commit is contained in:
Konstantin Porotchkin
Manish Pandey
parent
667893adb6
commit
718dbcac9c
6 changed files with 40 additions and 12 deletions
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@ -26,7 +26,7 @@ BL33 should be ``~/project/u-boot/u-boot.bin``
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*u-boot.bin* should be used and not *u-boot-spl.bin*
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Set MSS/SCP image path (mandatory only for A7K/8K/CN913x)
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Set MSS/SCP image path (mandatory only for A7K/8K/CN913x when MSS_SUPPORT=1)
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.. code:: shell
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@ -2284,7 +2284,6 @@ static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base,
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uint32_t comphy_mode)
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{
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uint32_t mask, data;
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uint8_t ap_nr, cp_nr;
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uintptr_t comphy_addr = comphy_addr =
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COMPHY_ADDR(comphy_base, comphy_index);
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@ -2301,10 +2300,16 @@ static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base,
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reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
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debug_exit();
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/* Start AP Firmware */
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mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
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mg_start_ap_fw(cp_nr, comphy_index);
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#if MSS_SUPPORT
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do {
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uint8_t ap_nr, cp_nr;
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/* start ap fw */
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mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
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mg_start_ap_fw(cp_nr, comphy_index);
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} while (0);
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#endif
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return 0;
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}
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@ -10,13 +10,14 @@ PLAT_COMMON_BASE := plat/marvell/armada/a8k/common
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MARVELL_DRV_BASE := drivers/marvell
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MARVELL_COMMON_BASE := plat/marvell/armada/common
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MARVELL_SVC_TEST := 0
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MARVELL_SVC_TEST := 0
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$(eval $(call add_define,MARVELL_SVC_TEST))
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ERRATA_A72_859971 := 1
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# Enable MSS support for a8k family
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MSS_SUPPORT := 1
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$(eval $(call add_define,MSS_SUPPORT))
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# Disable EL3 cache for power management
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BL31_CACHE_DISABLE := 0
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@ -114,12 +115,15 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \
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$(MARVELL_DRV_BASE)/cache_llc.c \
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$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
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$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
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$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \
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$(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \
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$(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c \
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$(MARVELL_DRV_BASE)/ddr_phy_access.c \
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drivers/rambus/trng_ip_76.c
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ifeq (${MSS_SUPPORT}, 1)
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MARVELL_DRV += $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c
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endif
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BL31_PORTING_SOURCES := $(BOARD_DIR)/board/marvell_plat_config.c
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ifeq ($(SYSTEM_POWER_SUPPORT),1)
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@ -142,6 +146,8 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \
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# Add trace functionality for PM
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BL31_SOURCES += $(PLAT_COMMON_BASE)/plat_pm_trace.c
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ifeq (${MSS_SUPPORT}, 1)
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# Force builds with BL2 image on a80x0 platforms
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ifndef SCP_BL2
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$(error "Error: SCP_BL2 image is mandatory for a8k family")
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@ -149,6 +155,7 @@ endif
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# MSS (SCP) build
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include $(PLAT_COMMON_BASE)/mss/mss_a8k.mk
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endif
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# BLE (ROM context execution code, AKA binary extension)
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BLE_PATH ?= $(PLAT_COMMON_BASE)/ble
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@ -16,8 +16,10 @@
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#include <marvell_pm.h>
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#include <mc_trustzone/mc_trustzone.h>
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#include <plat_marvell.h>
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#if MSS_SUPPORT
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#include <mss_ipc_drv.h>
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#include <mss_mem.h>
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#endif
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/* In Armada-8k family AP806/AP807, CP0 connected to PIDI
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* and CP1 connected to IHB via MCI #0
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@ -51,6 +53,7 @@ static void marvell_bl31_mpp_init(int cp)
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mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000);
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}
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#if MSS_SUPPORT
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void marvell_bl31_mss_init(void)
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{
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struct mss_pm_ctrl_block *mss_pm_crtl =
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@ -70,6 +73,7 @@ void marvell_bl31_mss_init(void)
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if (mss_pm_crtl->ipc_state == IPC_INITIALIZED)
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mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE);
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}
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#endif
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_Bool is_pm_fw_running(void)
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{
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@ -125,11 +129,12 @@ void bl31_plat_arch_setup(void)
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for (cp = 1; cp < CP_COUNT; cp++)
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mci_link_tune(cp - 1);
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#if MSS_SUPPORT
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/* initialize IPC between MSS and ATF */
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if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
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mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
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marvell_bl31_mss_init();
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#endif
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/* Configure GPIO */
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marvell_gpio_config();
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@ -18,7 +18,9 @@
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#include <armada_common.h>
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#include <marvell_pm.h>
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#if MSS_SUPPORT
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#include <mss_pm_ipc.h>
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#endif
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#include <plat_marvell.h>
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#include <plat_pm_trace.h>
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@ -396,6 +398,7 @@ static int a8k_pwr_domain_on(u_register_t mpidr)
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/* Power up CPU (CPUs 1-3 are powered off at start of BLE) */
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plat_marvell_cpu_powerup(mpidr);
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#if MSS_SUPPORT
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if (is_pm_fw_running()) {
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unsigned int target =
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((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2));
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@ -417,11 +420,12 @@ static int a8k_pwr_domain_on(u_register_t mpidr)
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/* trace message */
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PM_TRACE(TRACE_PWR_DOMAIN_ON | target);
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} else {
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} else
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#endif
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{
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/* proprietary CPU ON exection flow */
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plat_marvell_cpu_on(mpidr);
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}
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return 0;
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}
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@ -441,6 +445,7 @@ static int a8k_validate_ns_entrypoint(uintptr_t entrypoint)
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*/
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static void a8k_pwr_domain_off(const psci_power_state_t *target_state)
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{
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#if MSS_SUPPORT
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if (is_pm_fw_running()) {
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unsigned int idx = plat_my_core_pos();
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@ -466,6 +471,7 @@ static void a8k_pwr_domain_off(const psci_power_state_t *target_state)
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} else {
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INFO("%s: is not supported without SCP\n", __func__);
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}
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#endif
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}
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/* Get PM config to power off the SoC */
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@ -586,6 +592,7 @@ static void plat_marvell_power_off_prepare(struct power_off_method *pm_cfg,
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*/
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static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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#if MSS_SUPPORT
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if (is_pm_fw_running()) {
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unsigned int idx;
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@ -610,7 +617,9 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state)
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/* trace message */
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PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND);
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} else {
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} else
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#endif
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{
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uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
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INFO("Suspending to RAM\n");
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@ -8,10 +8,11 @@
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#if MSS_SUPPORT
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#include <mss_mem.h>
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#include <plat_pm_trace.h>
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#ifdef PM_TRACE_ENABLE
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#include <plat_pm_trace.h>
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/* core trace APIs */
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core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
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@ -90,3 +91,4 @@ void pm_core_3_trace(unsigned int trace)
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AP_MSS_ATF_TRACE_SIZE_MASK));
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}
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#endif /* PM_TRACE_ENABLE */
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#endif /* MSS_SUPPORT */
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