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fix(fvp): extract core id from mpidr for pwrc operations

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The ID field populated for every FVP PWRC register interface must be
computed from the affinity level values from MPIDR.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: If1474fd25704911f8f717dafb419a0734b99a4ec
This commit is contained in:
Madhukar Pappireddy 2023-07-31 23:22:02 -05:00
parent 96eb2dc4e3
commit 70bc74441b
1 changed files with 35 additions and 9 deletions
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44
drivers/arm/fvp/fvp_pwrc.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,22 +10,39 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
#define FVP_PWRC_ID_MASK U(0x00FFFFFF)
/*
* TODO: Someday there will be a generic power controller api. At the moment
* each platform has its own pwrc so just exporting functions is fine.
*/
ARM_INSTANTIATE_LOCK;
/*
* Core ID field is 24 bits wide and extracted from MPIDR.
* Bits[23:16] represent Affinity Level 2
* Bits[15:8] represent Affinity Level 1
* Bits[7:0] represent Affinity Level 0
*/
static unsigned int fvp_pwrc_core_id(u_register_t mpidr)
{
return (unsigned int)(mpidr & FVP_PWRC_ID_MASK);
}
unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
{
return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
unsigned int id = fvp_pwrc_core_id(mpidr);
return PSYSR_WK(fvp_pwrc_read_psysr(id));
}
unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
{
unsigned int rc;
unsigned int id = fvp_pwrc_core_id(mpidr);
arm_lock_get();
mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
mmio_write_32(PWRC_BASE + PSYSR_OFF, id);
rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
arm_lock_release();
return rc;
@ -33,38 +50,47 @@ unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
void fvp_pwrc_write_pponr(u_register_t mpidr)
{
unsigned int id = fvp_pwrc_core_id(mpidr);
arm_lock_get();
mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
mmio_write_32(PWRC_BASE + PPONR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_write_ppoffr(u_register_t mpidr)
{
unsigned int id = fvp_pwrc_core_id(mpidr);
arm_lock_get();
mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
mmio_write_32(PWRC_BASE + PPOFFR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_set_wen(u_register_t mpidr)
{
unsigned int id = fvp_pwrc_core_id(mpidr);
arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) (PWKUPR_WEN | mpidr));
(unsigned int) (PWKUPR_WEN | id));
arm_lock_release();
}
void fvp_pwrc_clr_wen(u_register_t mpidr)
{
unsigned int id = fvp_pwrc_core_id(mpidr);
arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) mpidr);
mmio_write_32(PWRC_BASE + PWKUPR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_write_pcoffr(u_register_t mpidr)
{
unsigned int id = fvp_pwrc_core_id(mpidr);
arm_lock_get();
mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
mmio_write_32(PWRC_BASE + PCOFFR_OFF, id);
arm_lock_release();
}