diff --git a/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi b/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi new file mode 100644 index 000000000..3917dc667 --- /dev/null +++ b/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +/* + * STM32MP25 LPDDR4 board configuration + * LPDDR4 1x16Gbits 1x32bits 1200MHz + * + * version 1 + * memclk 1200MHz (2x DFI clock) + * width 32 32: full width / 16: half width + * ranks 1 Single or Dual rank + * density 8Gbits (per 16bit channel) + * Addressing RBC row/bank interleaving + * DBI-RD No Read DBI + * DBI-WR No Write DBI + * RPST 1.5 Read postamble (ck) + * Per_bank_ref Yes + */ + +#define DDR_MEM_NAME "LPDDR4 1x16Gbits 1x32bits 1200MHz" +#define DDR_MEM_SPEED 1200000 +#define DDR_MEM_SIZE 0x80000000 + +#define DDR_MSTR 0x01080020 +#define DDR_MRCTRL0 0x00000030 +#define DDR_MRCTRL1 0x00000000 +#define DDR_MRCTRL2 0x00000000 +#define DDR_DERATEEN 0x00000203 +#define DDR_DERATEINT 0x0124F800 +#define DDR_DERATECTL 0x00000000 +#define DDR_PWRCTL 0x00000100 +#define DDR_PWRTMG 0x00130001 +#define DDR_HWLPCTL 0x00000002 +#define DDR_RFSHCTL0 0x00210014 +#define DDR_RFSHCTL1 0x00000000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x81240054 +#define DDR_RFSHTMG1 0x00360000 +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_CRCPARCTL1 0x00001000 +#define DDR_INIT0 0xC0020002 +#define DDR_INIT1 0x00010002 +#define DDR_INIT2 0x00000D00 +#define DDR_INIT3 0x00C40024 +#define DDR_INIT4 0x00310008 +#define DDR_INIT5 0x00100004 +#define DDR_INIT6 0x00660050 +#define DDR_INIT7 0x00050019 +#define DDR_DIMMCTL 0x00000000 +#define DDR_RANKCTL 0x0000066F +#define DDR_DRAMTMG0 0x1718141A +#define DDR_DRAMTMG1 0x00050524 +#define DDR_DRAMTMG2 0x060C1111 +#define DDR_DRAMTMG3 0x0090900C +#define DDR_DRAMTMG4 0x0B04060B +#define DDR_DRAMTMG5 0x02030909 +#define DDR_DRAMTMG6 0x02020007 +#define DDR_DRAMTMG7 0x00000302 +#define DDR_DRAMTMG8 0x03034405 +#define DDR_DRAMTMG9 0x0004040D +#define DDR_DRAMTMG10 0x001C180A +#define DDR_DRAMTMG11 0x440C021C +#define DDR_DRAMTMG12 0x1A020010 +#define DDR_DRAMTMG13 0x0B100002 +#define DDR_DRAMTMG14 0x000000AD +#define DDR_DRAMTMG15 0x00000000 +#define DDR_ZQCTL0 0x02580012 +#define DDR_ZQCTL1 0x01E0493E +#define DDR_ZQCTL2 0x00000000 +#define DDR_DFITMG0 0x0395820A +#define DDR_DFITMG1 0x000A0303 +#define DDR_DFILPCFG0 0x07F04111 +#define DDR_DFILPCFG1 0x000000F0 +#define DDR_DFIUPD0 0x4040000C +#define DDR_DFIUPD1 0x0040007F +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIMISC 0x00000041 +#define DDR_DFITMG2 0x0000150A +#define DDR_DFITMG3 0x00000000 +#define DDR_DBICTL 0x00000001 +#define DDR_DFIPHYMSTR 0x80000001 +#define DDR_ADDRMAP0 0x0000001F +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x070F0707 +#define DDR_ADDRMAP6 0x07070707 +#define DDR_ADDRMAP7 0x00000F0F +#define DDR_ADDRMAP8 0x00003F3F +#define DDR_ADDRMAP9 0x07070707 +#define DDR_ADDRMAP10 0x07070707 +#define DDR_ADDRMAP11 0x00000007 +#define DDR_ODTCFG 0x04000400 +#define DDR_ODTMAP 0x00000000 +#define DDR_SCHED 0x00001B00 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x04000200 +#define DDR_PERFLPR1 0x08000080 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_SWCTL 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000000 +#define DDR_PCFGR_0 0x00004100 +#define DDR_PCFGW_0 0x00004100 +#define DDR_PCTRL_0 0x00000000 +#define DDR_PCFGQOS0_0 0x0021000C +#define DDR_PCFGQOS1_0 0x01000080 +#define DDR_PCFGWQOS0_0 0x01100C07 +#define DDR_PCFGWQOS1_0 0x04000200 +#define DDR_PCFGR_1 0x00004100 +#define DDR_PCFGW_1 0x00004100 +#define DDR_PCTRL_1 0x00000000 +#define DDR_PCFGQOS0_1 0x00100007 +#define DDR_PCFGQOS1_1 0x01000080 +#define DDR_PCFGWQOS0_1 0x01100C07 +#define DDR_PCFGWQOS1_1 0x04000200 + +#define DDR_UIB_DRAMTYPE 0x00000002 +#define DDR_UIB_DIMMTYPE 0x00000004 +#define DDR_UIB_LP4XMODE 0x00000000 +#define DDR_UIB_NUMDBYTE 0x00000004 +#define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000002 +#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000002 +#define DDR_UIB_NUMANIB 0x00000008 +#define DDR_UIB_NUMRANK_DFI0 0x00000001 +#define DDR_UIB_NUMRANK_DFI1 0x00000001 +#define DDR_UIB_DRAMDATAWIDTH 0x00000010 +#define DDR_UIB_NUMPSTATES 0x00000001 +#define DDR_UIB_FREQUENCY_0 0x000004B0 +#define DDR_UIB_PLLBYPASS_0 0x00000000 +#define DDR_UIB_DFIFREQRATIO_0 0x00000001 +#define DDR_UIB_DFI1EXISTS 0x00000001 +#define DDR_UIB_TRAIN2D 0x00000000 +#define DDR_UIB_HARDMACROVER 0x00000003 +#define DDR_UIB_READDBIENABLE_0 0x00000000 +#define DDR_UIB_DFIMODE 0x00000000 + +#define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000 +#define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000001 +#define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000001 +#define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000 +#define DDR_UIA_EXTCALRESVAL 0x00000000 +#define DDR_UIA_IS2TTIMING_0 0x00000000 +#define DDR_UIA_ODTIMPEDANCE_0 0x00000035 +#define DDR_UIA_TXIMPEDANCE_0 0x0000003C +#define DDR_UIA_ATXIMPEDANCE 0x0000001E +#define DDR_UIA_MEMALERTEN 0x00000000 +#define DDR_UIA_MEMALERTPUIMP 0x00000000 +#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000 +#define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000 +#define DDR_UIA_DISDYNADRTRI_0 0x00000001 +#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A +#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005 +#define DDR_UIA_WDQSEXT 0x00000000 +#define DDR_UIA_CALINTERVAL 0x00000009 +#define DDR_UIA_CALONCE 0x00000000 +#define DDR_UIA_LP4RL_0 0x00000004 +#define DDR_UIA_LP4WL_0 0x00000004 +#define DDR_UIA_LP4WLS_0 0x00000000 +#define DDR_UIA_LP4DBIRD_0 0x00000000 +#define DDR_UIA_LP4DBIWR_0 0x00000000 +#define DDR_UIA_LP4NWR_0 0x00000004 +#define DDR_UIA_LP4LOWPOWERDRV 0x00000000 +#define DDR_UIA_DRAMBYTESWAP 0x00000000 +#define DDR_UIA_RXENBACKOFF 0x00000000 +#define DDR_UIA_TRAINSEQUENCECTRL 0x00000000 +#define DDR_UIA_SNPSUMCTLOPT 0x00000000 +#define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000 +#define DDR_UIA_TXSLEWRISEDQ_0 0x0000000F +#define DDR_UIA_TXSLEWFALLDQ_0 0x0000000F +#define DDR_UIA_TXSLEWRISEAC 0x0000000F +#define DDR_UIA_TXSLEWFALLAC 0x0000000F +#define DDR_UIA_DISABLERETRAINING 0x00000000 +#define DDR_UIA_DISABLEPHYUPDATE 0x00000001 +#define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000 +#define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001 +#define DDR_UIA_PHYINITSEQUENCENUM 0x00000000 +#define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000 +#define DDR_UIA_PHYVREF 0x00000014 +#define DDR_UIA_SEQUENCECTRL_0 0x0000131F + +#define DDR_UIM_MR0_0 0x00000000 +#define DDR_UIM_MR1_0 0x000000C4 +#define DDR_UIM_MR2_0 0x00000024 +#define DDR_UIM_MR3_0 0x00000031 +#define DDR_UIM_MR4_0 0x00000000 +#define DDR_UIM_MR5_0 0x00000000 +#define DDR_UIM_MR6_0 0x00000000 +#define DDR_UIM_MR11_0 0x00000066 +#define DDR_UIM_MR12_0 0x00000050 +#define DDR_UIM_MR13_0 0x00000008 +#define DDR_UIM_MR14_0 0x00000019 +#define DDR_UIM_MR22_0 0x00000005 + +#define DDR_UIS_SWIZZLE_0 0x00000003 +#define DDR_UIS_SWIZZLE_1 0x00000002 +#define DDR_UIS_SWIZZLE_2 0x00000000 +#define DDR_UIS_SWIZZLE_3 0x00000001 +#define DDR_UIS_SWIZZLE_4 0x00000006 +#define DDR_UIS_SWIZZLE_5 0x00000007 +#define DDR_UIS_SWIZZLE_6 0x00000005 +#define DDR_UIS_SWIZZLE_7 0x00000004 +#define DDR_UIS_SWIZZLE_8 0x00000005 +#define DDR_UIS_SWIZZLE_9 0x00000004 +#define DDR_UIS_SWIZZLE_10 0x00000007 +#define DDR_UIS_SWIZZLE_11 0x00000006 +#define DDR_UIS_SWIZZLE_12 0x00000000 +#define DDR_UIS_SWIZZLE_13 0x00000003 +#define DDR_UIS_SWIZZLE_14 0x00000002 +#define DDR_UIS_SWIZZLE_15 0x00000001 +#define DDR_UIS_SWIZZLE_16 0x00000005 +#define DDR_UIS_SWIZZLE_17 0x00000007 +#define DDR_UIS_SWIZZLE_18 0x00000006 +#define DDR_UIS_SWIZZLE_19 0x00000004 +#define DDR_UIS_SWIZZLE_20 0x00000000 +#define DDR_UIS_SWIZZLE_21 0x00000001 +#define DDR_UIS_SWIZZLE_22 0x00000003 +#define DDR_UIS_SWIZZLE_23 0x00000002 +#define DDR_UIS_SWIZZLE_24 0x00000007 +#define DDR_UIS_SWIZZLE_25 0x00000004 +#define DDR_UIS_SWIZZLE_26 0x00000005 +#define DDR_UIS_SWIZZLE_27 0x00000006 +#define DDR_UIS_SWIZZLE_28 0x00000002 +#define DDR_UIS_SWIZZLE_29 0x00000003 +#define DDR_UIS_SWIZZLE_30 0x00000001 +#define DDR_UIS_SWIZZLE_31 0x00000000 +#define DDR_UIS_SWIZZLE_32 0x00000000 +#define DDR_UIS_SWIZZLE_33 0x00000001 +#define DDR_UIS_SWIZZLE_34 0x00000002 +#define DDR_UIS_SWIZZLE_35 0x00000003 +#define DDR_UIS_SWIZZLE_36 0x00000004 +#define DDR_UIS_SWIZZLE_37 0x00000005 +#define DDR_UIS_SWIZZLE_38 0x00000000 +#define DDR_UIS_SWIZZLE_39 0x00000001 +#define DDR_UIS_SWIZZLE_40 0x00000002 +#define DDR_UIS_SWIZZLE_41 0x00000003 +#define DDR_UIS_SWIZZLE_42 0x00000004 +#define DDR_UIS_SWIZZLE_43 0x00000005 + +#include "stm32mp25-ddr.dtsi" diff --git a/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi b/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi new file mode 100644 index 000000000..53d6b7d1d --- /dev/null +++ b/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +/* + * STM32MP25 LPDDR4 board configuration + * LPDDR4 1x32Gbits 1x32bits 1200MHz + * + * version 2 + * memclk 1200MHz (2x DFI clock) + * width 32 32: full width / 16: half width + * ranks 1 Single or Dual rank + * density 16Gbits (per 16bit channel) + * Addressing RBC row/bank interleaving + * DBI-RD No Read DBI + * DBI-WR No Write DBI + * RPST 1.5 Read postamble (ck) + * Per_bank_ref Yes + */ + +#define DDR_MEM_NAME "LPDDR4 1x32Gbits 1x32bits 1200MHz" +#define DDR_MEM_SPEED 1200000 +#define DDR_MEM_SIZE 0x100000000 + +#define DDR_MSTR 0x01080020 +#define DDR_MRCTRL0 0x00000030 +#define DDR_MRCTRL1 0x00000000 +#define DDR_MRCTRL2 0x00000000 +#define DDR_DERATEEN 0x00000203 +#define DDR_DERATEINT 0x0124F800 +#define DDR_DERATECTL 0x00000000 +#define DDR_PWRCTL 0x00000100 +#define DDR_PWRTMG 0x00130001 +#define DDR_HWLPCTL 0x00000002 +#define DDR_RFSHCTL0 0x00210014 +#define DDR_RFSHCTL1 0x00000000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x81240072 +#define DDR_RFSHTMG1 0x00360000 +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_CRCPARCTL1 0x00001000 +#define DDR_INIT0 0xC0020002 +#define DDR_INIT1 0x00010002 +#define DDR_INIT2 0x00000D00 +#define DDR_INIT3 0x00C40024 +#define DDR_INIT4 0x00310008 +#define DDR_INIT5 0x00100004 +#define DDR_INIT6 0x00660047 +#define DDR_INIT7 0x00050047 +#define DDR_DIMMCTL 0x00000000 +#define DDR_RANKCTL 0x0000066F +#define DDR_RANKCTL1 0x00000011 +#define DDR_DRAMTMG0 0x1718141A +#define DDR_DRAMTMG1 0x00050524 +#define DDR_DRAMTMG2 0x060C1111 +#define DDR_DRAMTMG3 0x0090900C +#define DDR_DRAMTMG4 0x0B04060B +#define DDR_DRAMTMG5 0x02030909 +#define DDR_DRAMTMG6 0x02020007 +#define DDR_DRAMTMG7 0x00000302 +#define DDR_DRAMTMG8 0x03034405 +#define DDR_DRAMTMG9 0x0004040D +#define DDR_DRAMTMG10 0x001C180A +#define DDR_DRAMTMG11 0x440C021C +#define DDR_DRAMTMG12 0x1A020010 +#define DDR_DRAMTMG13 0x0B100002 +#define DDR_DRAMTMG14 0x000000E9 +#define DDR_DRAMTMG15 0x00000000 +#define DDR_ZQCTL0 0x02580012 +#define DDR_ZQCTL1 0x01E0493E +#define DDR_ZQCTL2 0x00000000 +#define DDR_DFITMG0 0x0395820A +#define DDR_DFITMG1 0x000A0303 +#define DDR_DFILPCFG0 0x07F04111 +#define DDR_DFILPCFG1 0x000000F0 +#define DDR_DFIUPD0 0x4040000C +#define DDR_DFIUPD1 0x0040007F +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIMISC 0x00000041 +#define DDR_DFITMG2 0x0000150A +#define DDR_DFITMG3 0x00000000 +#define DDR_DBICTL 0x00000001 +#define DDR_DFIPHYMSTR 0x80000001 +#define DDR_ADDRMAP0 0x0000001F +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x070F0707 +#define DDR_ADDRMAP6 0x07070707 +#define DDR_ADDRMAP7 0x00000F07 +#define DDR_ADDRMAP8 0x00003F3F +#define DDR_ADDRMAP9 0x07070707 +#define DDR_ADDRMAP10 0x07070707 +#define DDR_ADDRMAP11 0x00000007 +#define DDR_ODTCFG 0x04000400 +#define DDR_ODTMAP 0x00000000 +#define DDR_SCHED 0x80001B00 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x04000200 +#define DDR_PERFLPR1 0x08000080 +#define DDR_PERFWR1 0x08000400 +#define DDR_SCHED3 0x04040208 +#define DDR_SCHED4 0x08400810 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_SWCTL 0x00000000 +#define DDR_SWCTLSTATIC 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000000 +#define DDR_PCFGR_0 0x00704100 +#define DDR_PCFGW_0 0x00004100 +#define DDR_PCTRL_0 0x00000000 +#define DDR_PCFGQOS0_0 0x0021000C +#define DDR_PCFGQOS1_0 0x01000080 +#define DDR_PCFGWQOS0_0 0x01100C07 +#define DDR_PCFGWQOS1_0 0x04000200 +#define DDR_PCFGR_1 0x00704100 +#define DDR_PCFGW_1 0x00004100 +#define DDR_PCTRL_1 0x00000000 +#define DDR_PCFGQOS0_1 0x00100007 +#define DDR_PCFGQOS1_1 0x01000080 +#define DDR_PCFGWQOS0_1 0x01100C07 +#define DDR_PCFGWQOS1_1 0x04000200 + +#define DDR_UIB_DRAMTYPE 0x00000002 +#define DDR_UIB_DIMMTYPE 0x00000004 +#define DDR_UIB_LP4XMODE 0x00000000 +#define DDR_UIB_NUMDBYTE 0x00000004 +#define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000002 +#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000002 +#define DDR_UIB_NUMANIB 0x00000008 +#define DDR_UIB_NUMRANK_DFI0 0x00000001 +#define DDR_UIB_NUMRANK_DFI1 0x00000001 +#define DDR_UIB_DRAMDATAWIDTH 0x00000010 +#define DDR_UIB_NUMPSTATES 0x00000001 +#define DDR_UIB_FREQUENCY_0 0x000004B0 +#define DDR_UIB_PLLBYPASS_0 0x00000000 +#define DDR_UIB_DFIFREQRATIO_0 0x00000001 +#define DDR_UIB_DFI1EXISTS 0x00000001 +#define DDR_UIB_TRAIN2D 0x00000000 +#define DDR_UIB_HARDMACROVER 0x00000003 +#define DDR_UIB_READDBIENABLE_0 0x00000000 +#define DDR_UIB_DFIMODE 0x00000000 + +#define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000 +#define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000001 +#define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000001 +#define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000 +#define DDR_UIA_EXTCALRESVAL 0x00000000 +#define DDR_UIA_IS2TTIMING_0 0x00000000 +#define DDR_UIA_ODTIMPEDANCE_0 0x00000035 +#define DDR_UIA_TXIMPEDANCE_0 0x00000028 +#define DDR_UIA_ATXIMPEDANCE 0x00000028 +#define DDR_UIA_MEMALERTEN 0x00000000 +#define DDR_UIA_MEMALERTPUIMP 0x00000000 +#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000 +#define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000 +#define DDR_UIA_DISDYNADRTRI_0 0x00000001 +#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A +#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005 +#define DDR_UIA_WDQSEXT 0x00000000 +#define DDR_UIA_CALINTERVAL 0x00000009 +#define DDR_UIA_CALONCE 0x00000000 +#define DDR_UIA_LP4RL_0 0x00000004 +#define DDR_UIA_LP4WL_0 0x00000004 +#define DDR_UIA_LP4WLS_0 0x00000000 +#define DDR_UIA_LP4DBIRD_0 0x00000000 +#define DDR_UIA_LP4DBIWR_0 0x00000000 +#define DDR_UIA_LP4NWR_0 0x00000004 +#define DDR_UIA_LP4LOWPOWERDRV 0x00000000 +#define DDR_UIA_DRAMBYTESWAP 0x00000000 +#define DDR_UIA_RXENBACKOFF 0x00000000 +#define DDR_UIA_TRAINSEQUENCECTRL 0x00000000 +#define DDR_UIA_SNPSUMCTLOPT 0x00000000 +#define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000 +#define DDR_UIA_TXSLEWRISEDQ_0 0x0000000F +#define DDR_UIA_TXSLEWFALLDQ_0 0x0000000F +#define DDR_UIA_TXSLEWRISEAC 0x0000000F +#define DDR_UIA_TXSLEWFALLAC 0x0000000F +#define DDR_UIA_DISABLERETRAINING 0x00000000 +#define DDR_UIA_DISABLEPHYUPDATE 0x00000001 +#define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000 +#define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001 +#define DDR_UIA_PHYINITSEQUENCENUM 0x00000000 +#define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000 +#define DDR_UIA_PHYVREF 0x00000014 +#define DDR_UIA_SEQUENCECTRL_0 0x0000131F + +#define DDR_UIM_MR0_0 0x00000000 +#define DDR_UIM_MR1_0 0x000000C4 +#define DDR_UIM_MR2_0 0x00000024 +#define DDR_UIM_MR3_0 0x00000031 +#define DDR_UIM_MR4_0 0x00000000 +#define DDR_UIM_MR5_0 0x00000000 +#define DDR_UIM_MR6_0 0x00000000 +#define DDR_UIM_MR11_0 0x00000066 +#define DDR_UIM_MR12_0 0x00000047 +#define DDR_UIM_MR13_0 0x00000008 +#define DDR_UIM_MR14_0 0x00000047 +#define DDR_UIM_MR22_0 0x00000005 + +#define DDR_UIS_SWIZZLE_0 0x00000003 +#define DDR_UIS_SWIZZLE_1 0x00000002 +#define DDR_UIS_SWIZZLE_2 0x00000000 +#define DDR_UIS_SWIZZLE_3 0x00000001 +#define DDR_UIS_SWIZZLE_4 0x00000006 +#define DDR_UIS_SWIZZLE_5 0x00000007 +#define DDR_UIS_SWIZZLE_6 0x00000005 +#define DDR_UIS_SWIZZLE_7 0x00000004 +#define DDR_UIS_SWIZZLE_8 0x00000005 +#define DDR_UIS_SWIZZLE_9 0x00000004 +#define DDR_UIS_SWIZZLE_10 0x00000007 +#define DDR_UIS_SWIZZLE_11 0x00000006 +#define DDR_UIS_SWIZZLE_12 0x00000000 +#define DDR_UIS_SWIZZLE_13 0x00000003 +#define DDR_UIS_SWIZZLE_14 0x00000002 +#define DDR_UIS_SWIZZLE_15 0x00000001 +#define DDR_UIS_SWIZZLE_16 0x00000005 +#define DDR_UIS_SWIZZLE_17 0x00000007 +#define DDR_UIS_SWIZZLE_18 0x00000006 +#define DDR_UIS_SWIZZLE_19 0x00000004 +#define DDR_UIS_SWIZZLE_20 0x00000000 +#define DDR_UIS_SWIZZLE_21 0x00000001 +#define DDR_UIS_SWIZZLE_22 0x00000003 +#define DDR_UIS_SWIZZLE_23 0x00000002 +#define DDR_UIS_SWIZZLE_24 0x00000007 +#define DDR_UIS_SWIZZLE_25 0x00000004 +#define DDR_UIS_SWIZZLE_26 0x00000005 +#define DDR_UIS_SWIZZLE_27 0x00000006 +#define DDR_UIS_SWIZZLE_28 0x00000002 +#define DDR_UIS_SWIZZLE_29 0x00000003 +#define DDR_UIS_SWIZZLE_30 0x00000001 +#define DDR_UIS_SWIZZLE_31 0x00000000 +#define DDR_UIS_SWIZZLE_32 0x00000000 +#define DDR_UIS_SWIZZLE_33 0x00000001 +#define DDR_UIS_SWIZZLE_34 0x00000002 +#define DDR_UIS_SWIZZLE_35 0x00000003 +#define DDR_UIS_SWIZZLE_36 0x00000004 +#define DDR_UIS_SWIZZLE_37 0x00000005 +#define DDR_UIS_SWIZZLE_38 0x00000000 +#define DDR_UIS_SWIZZLE_39 0x00000001 +#define DDR_UIS_SWIZZLE_40 0x00000002 +#define DDR_UIS_SWIZZLE_41 0x00000003 +#define DDR_UIS_SWIZZLE_42 0x00000004 +#define DDR_UIS_SWIZZLE_43 0x00000005 + +#include "stm32mp25-ddr.dtsi" diff --git a/fdts/stm32mp25-pinctrl.dtsi b/fdts/stm32mp25-pinctrl.dtsi index a22c8239b..b2ca96248 100644 --- a/fdts/stm32mp25-pinctrl.dtsi +++ b/fdts/stm32mp25-pinctrl.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) /* - * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved + * Copyright (C) 2023-2025, STMicroelectronics - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ #include @@ -37,6 +37,26 @@ }; }; + /omit-if-no-ref/ + sdmmc1_b4_pins_b: sdmmc1-b4-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { @@ -45,13 +65,13 @@ , /* SDMMC2_D2 */ , /* SDMMC2_D3 */ ; /* SDMMC2_CMD */ - slew-rate = <2>; + slew-rate = <1>; drive-push-pull; bias-pull-up; }; pins2 { pinmux = ; /* SDMMC2_CK */ - slew-rate = <3>; + slew-rate = <2>; drive-push-pull; bias-pull-up; }; @@ -64,7 +84,7 @@ , /* SDMMC2_D5 */ , /* SDMMC2_D6 */ ; /* SDMMC2_D7 */ - slew-rate = <2>; + slew-rate = <1>; drive-push-pull; bias-pull-up; }; diff --git a/fdts/stm32mp257f-dk-ca35tdcid-fw-config.dtsi b/fdts/stm32mp257f-dk-ca35tdcid-fw-config.dtsi new file mode 100644 index 000000000..9637e1ab2 --- /dev/null +++ b/fdts/stm32mp257f-dk-ca35tdcid-fw-config.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + */ + +/* + * STM32MP25 tf-a firmware config + * Project : open + * Generated by XLmx tool version 2.2 - 3/6/2024 11:20:07 AM + */ + +/ { + dtb-registry { + soc_fw-config { + load-address = <0x0 0x81fc0000>; + max-size = <0x40000>; + }; + tos_fw { + load-address = <0x0 0x82000000>; + max-size = <0x2000000>; + }; + }; +}; diff --git a/fdts/stm32mp257f-dk-ca35tdcid-rcc.dtsi b/fdts/stm32mp257f-dk-ca35tdcid-rcc.dtsi new file mode 100644 index 000000000..dd38a52e9 --- /dev/null +++ b/fdts/stm32mp257f-dk-ca35tdcid-rcc.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics. + */ + +/* + * STM32MP25 Clock tree device tree configuration + * Project : open + * Generated by XLmx tool version 2.2 - 3/6/2024 11:20:07 AM + */ + +&clk_hse { + clock-frequency = <40000000>; +}; + +&clk_hsi { + clock-frequency = <64000000>; +}; + +&clk_lse { + clock-frequency = <32768>; +}; + +&clk_lsi { + clock-frequency = <32000>; +}; + +&clk_msi { + clock-frequency = <16000000>; +}; + +&rcc { + st,busclk = < + DIV_CFG(DIV_LSMCU, 1) + DIV_CFG(DIV_APB1, 0) + DIV_CFG(DIV_APB2, 0) + DIV_CFG(DIV_APB3, 0) + DIV_CFG(DIV_APB4, 0) + DIV_CFG(DIV_APBDBG, 0) + >; + + st,flexgen = < + FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) + FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) + FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) + FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) + >; + + st,kerclk = < + MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) + MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) + >; + + pll1: st,pll-1 { + st,pll = <&pll1_cfg_1200Mhz>; + + pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { + cfg = <30 1 1 1>; + src = ; + }; + }; + + pll2: st,pll-2 { + st,pll = <&pll2_cfg_600Mhz>; + + pll2_cfg_600Mhz: pll2-cfg-600Mhz { + cfg = <30 1 1 2>; + src = ; + }; + }; + + pll4: st,pll-4 { + st,pll = <&pll4_cfg_1200Mhz>; + + pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { + cfg = <30 1 1 1>; + src = ; + }; + }; + + pll5: st,pll-5 { + st,pll = <&pll5_cfg_532Mhz>; + + pll5_cfg_532Mhz: pll5-cfg-532Mhz { + cfg = <133 5 1 2>; + src = ; + }; + }; +}; diff --git a/fdts/stm32mp257f-dk-fw-config.dts b/fdts/stm32mp257f-dk-fw-config.dts new file mode 100644 index 000000000..67f8e30cf --- /dev/null +++ b/fdts/stm32mp257f-dk-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2025, STMicroelectronics - All Rights Reserved + */ + +#include "stm32mp25-fw-config.dtsi" +#include "stm32mp257f-dk-ca35tdcid-fw-config.dtsi" diff --git a/fdts/stm32mp257f-dk.dts b/fdts/stm32mp257f-dk.dts new file mode 100644 index 000000000..ae18d6ab4 --- /dev/null +++ b/fdts/stm32mp257f-dk.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp257f-dk-ca35tdcid-rcc.dtsi" +#include "stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxal-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-DK Discovery Board"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x00000000>; + }; + + shadow-prov { + compatible = "st,provisioning"; + + hconf1_prov { + nvmem-cells = <&hconf1_otp>; + st,shadow-value = <0x00018000>; + }; + }; +}; + +&bsec { + board_id: board-id@3d8 { + reg = <0x3d8 0x4>; + }; +}; + +&ddr { + vdd1-supply = <&vdd1_ddr>; + vdd2-supply = <&vdd2_ddr>; + vddq-supply = <&vdd2_ddr>; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pmic2: stpmic@33 { + compatible = "st,stpmic2"; + reg = <0x33>; + status = "okay"; + + regulators { + compatible = "st,stpmic2-regulators"; + + vddcpu: buck1 { + regulator-name = "vddcpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <910000>; + regulator-always-on; + }; + vddcore: buck2 { + regulator-name = "vddcore"; + regulator-min-microvolt = <820000>; + regulator-max-microvolt = <820000>; + regulator-always-on; + }; + vddgpu: buck3 { + regulator-name = "vddgpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + vddio_pmic: buck4 { + regulator-name = "vddio_pmic"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + v1v8: buck5 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + vdd2_ddr: buck6 { + regulator-name = "vdd2_ddr"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + v3v3: buck7 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdda1v8_aon: ldo1 { + regulator-name = "vdda1v8_aon"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + vdd_emmc: ldo2 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd1_ddr: ldo3 { + regulator-name = "vdd1_ddr"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + }; + vdd3v3_usb: ldo4 { + regulator-name = "vdd3v3_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + v5v_hdmi: ldo5 { + regulator-name = "v5v_hdmi"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + }; + vdd_sdcard: ldo7 { + regulator-name = "vdd_sdcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vddio_sdcard: ldo8 { + regulator-name = "vddio_sdcard"; + st,regulator-bypass-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&pwr { + vddio1: vddio1 { + vddio1-supply = <&vddio_sdcard>; + }; + vddio2: vddio2 { + vddio2-supply = <&v1v8>; + }; + vddio3: vddio3 { + vddio3-supply = <&vddio_pmic>; + }; + vddio4: vddio4 { + vddio4-supply = <&vddio_pmic>; + }; + vddio: vddio { + vdd-supply = <&vddio_pmic>; + }; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sdcard>; + vqmmc-supply = <&vddio1>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&vdd_emmc>; + vqmmc-supply = <&vddio2>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default"; + pinctrl-0 = <&usart2_pins_a>; + status = "okay"; +};