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feat(ethos-n): add support to set up NSAID
For the TZC to allow the Arm(R) Ethos(TM)-N NPU to access the buffers allocated in a protected memory region, it must include the correct NSAID for that region in its transactions to the memory. This change updates the SiP service to configure the NSAIDs specified by a platform define. When doing a protected access the SiP service now configures the NSAIDs specified by the platform define. For unprotected access the NSAID is set to zero. Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com> Signed-off-by: Rob Hughes <robert.hughes@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I3360ef33705162aba5c67670386922420869e331
This commit is contained in:
Rajasekaran Kalidoss
Joanna Farley
parent
0165ddd7c0
commit
70a296ee86
3 changed files with 62 additions and 3 deletions
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@ -574,6 +574,19 @@ optionally be defined:
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PLAT_PARTITION_BLOCK_SIZE := 4096
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$(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
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If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support
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enabled, the following constants must also be defined.
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- **ARM_ETHOSN_NPU_PROT_FW_NSAID**
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
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access the protected memory that contains the NPU's firmware.
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- **ARM_ETHOSN_NPU_PROT_DATA_NSAID**
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Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
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access the protected memory that contains inference data.
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The following constant is optional. It should be defined to override the default
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behaviour of the ``assert()`` function (for example, to save memory).
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@ -15,6 +15,8 @@
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#include <lib/utils_def.h>
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#include <plat/arm/common/fconf_ethosn_getter.h>
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#include <platform_def.h>
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/*
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* Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available
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*/
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@ -47,9 +49,16 @@
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#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
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#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
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#define SEC_NSAID_REG_BASE U(0x3004)
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#define SEC_NSAID_OFFSET U(0x1000)
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#define SEC_MMUSID_REG_BASE U(0x3008)
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#define SEC_MMUSID_OFFSET U(0x1000)
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#define INPUT_STREAM_INDEX U(0x6)
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#define INTERMEDIATE_STREAM_INDEX U(0x7)
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#define OUTPUT_STREAM_INDEX U(0x8)
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static bool ethosn_get_device_and_core(uintptr_t core_addr,
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const struct ethosn_device_t **dev_match,
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const struct ethosn_core_t **core_match)
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@ -75,6 +84,29 @@ static bool ethosn_get_device_and_core(uintptr_t core_addr,
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return false;
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}
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#if ARM_ETHOSN_NPU_TZMP1
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static void ethosn_configure_stream_nsaid(const struct ethosn_core_t *core,
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bool is_protected)
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{
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size_t i;
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uint32_t streams[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
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if (is_protected) {
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streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_DATA_NSAID;
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streams[INTERMEDIATE_STREAM_INDEX] =
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ARM_ETHOSN_NPU_PROT_DATA_NSAID;
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streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_DATA_NSAID;
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}
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for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
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const uintptr_t reg_addr = SEC_NSAID_REG_BASE +
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(SEC_NSAID_OFFSET * i);
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mmio_write_32(ETHOSN_CORE_SEC_REG(core->addr, reg_addr),
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streams[i]);
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}
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}
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#endif
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static void ethosn_configure_smmu_streams(const struct ethosn_device_t *device,
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const struct ethosn_core_t *core,
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uint32_t asset_alloc_idx)
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@ -163,7 +195,7 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t core_addr,
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u_register_t asset_alloc_idx,
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u_register_t reset_type,
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u_register_t x4,
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u_register_t is_protected,
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void *cookie,
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void *handle,
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u_register_t flags)
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@ -184,7 +216,7 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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core_addr &= 0xFFFFFFFF;
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asset_alloc_idx &= 0xFFFFFFFF;
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reset_type &= 0xFFFFFFFF;
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x4 &= 0xFFFFFFFF;
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is_protected &= 0xFFFFFFFF;
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}
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if (!is_ethosn_fid(smc_fid) || (fid > ETHOSN_FNUM_IS_SLEEPING)) {
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@ -238,6 +270,11 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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if (!device->has_reserved_memory) {
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ethosn_configure_smmu_streams(device, core,
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asset_alloc_idx);
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#if ARM_ETHOSN_NPU_TZMP1
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ethosn_configure_stream_nsaid(core,
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is_protected);
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#endif
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}
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ethosn_delegate_to_ns(core->addr);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -19,6 +19,9 @@
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#include <plat/common/common_def.h>
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#include "../juno_def.h"
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#ifdef JUNO_ETHOSN_TZMP1
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#include "../juno_ethosn_tzmp1_def.h"
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#endif
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/* Required platform porting definitions */
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/* Juno supports system power domain */
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@ -310,4 +313,10 @@
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/* Number of SCMI channels on the platform */
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#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
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/* Protected memory NSAIDs for the Arm(R) Ethos(TM)-N NPU driver */
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#ifdef JUNO_ETHOSN_TZMP1
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#define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
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#define ARM_ETHOSN_NPU_PROT_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_PROT
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#endif
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#endif /* PLATFORM_DEF_H */
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